Harris Corporation

Intersil Americas Inc.

Other

Salomon Vulih

Harold Allen Wittlinger

John A Olmstead

William Brandes Shearon

Stephen J Glica

Thomas D Housten

Raymond L Giordano

Donald R Preslar

George R Briggs

Robert H Isham

Stanley F Wietecha

Douglas M Mattingly

Timothy Maher

A controller and methodology for a power supply are disclosed. The controller includes output channels for providing a pulse width modulation (PWM) voltage signal for driving a load, for example, a microprocessor. Each channel provides a portion of the PWM signal. The controller receives user input information and uses that information to automatically determine window sizes. A window size defines the maximum output current level for a given window. The controller uses feedback signals to determine the current being drawn by the load, and selects the number of windows and channels that are needed to adequately provide that current. The controller selectively activates and deactivates the output channels accordingly. In response a change in the user input information the controller automatically adjusts the window sizes.

Programmable power supply controller and methodology for automatic phase adjustment of a PWM output signal

A power supply switching circuit arrangement is configured to provide a relatively smooth (low noise) power supply switch-over during the transition between active and quiescent modes. Complementary inputs of an operational amplifier are selective coupled to feedback paths to the amplifier and the power supply switching circuit arrangement, so as to bias a switching transistor during system active mode at a value that is just slightly below the turn-on voltage of the transistor. This means that turning on the switching transistor for the purpose of providing quiescent mode powering of the utility device requires only a small transition in control voltage from an active mode 'almost turned-on' level.

Smooth voltage regulation transition circuit having fast recovery

The integrated circuit includes a power driving device, and a pilot device for sensing current through the power driving device. The pilot device includes a composite pilot having a plurality of series connected transistors and which is at least active while the power driving device is in a linear mode, and a secondary pilot which is active while the power driving device is in a saturation mode. Also, a control circuit activates the secondary pilot.

Integrated circuit with current sense circuit and associated methods

The integrated circuit includes a power FET for generating an output voltage, a pilot FET for sensing current through the power driving device and generating a reference voltage, and an amplifier circuit for comparing the reference voltage of the pilot device with the output voltage of the power driving device. The amplifier circuit includes a differential pair of matched bipolar junction transistors (BJTs) having a common base. A first BJT of the differential pair being diode-connected. The amplifier circuit controls the gates of the power FET and the pilot FET.

Integrated circuit with current-limited power output and associated method

An oscillator includes a first sawtooth waveform generator for generating a first sawtooth waveform having a selectively started ramp portion and a second sawtooth waveform generator for generating a second sawtooth waveform having a selectively started ramp portion. A controller is also included for alternatingly controlling the first and second sawtooth waveform generators so that a transition to the ramp portion of one sawtooth waveform is based upon determining the ramp portion of the other sawtooth waveform reaching a trip point. The controller also sets the trip point substantially independent of a supply voltage so that the oscillator has reduced sensitivity to supply voltage changes.

Oscillator having reduced sensitivity to supply voltage changes

A charge pump circuit includes a plurality of pumping capacitors, a plurality of switches connected to the pumping capacitors, and a controller for generating first and second sets of switch control signals for controlling the switches so that the pumping capacitors generate either an increased or a negative output voltage. The controller includes a clock having first outputs for the first set of switch control signals, a transient clamp network having second outputs for the second set of switch control signals, and a respective level shifting capacitor connected between each first output and a corresponding second output and cooperating with the transient clamp network so that the second set of signals is level shifted from the first set.

Cascadable, high efficiency charge pump circuit and related methods

In systems embodying the invention, circuitry responsive to first and second, complementary, input signals controls the application of the input signals to a positive signal integrator and to a negative signal integrator. When the amplitude of the input signals is greater than a predetermined value, the one of the two input signals which is positive relative to the other is applied to the positive signal integrator and the other one of the two input signals is applied to the negative signal integrator. When the amplitude of the input signals is smaller than a predetermined level, the circuitry causes the periodic application of the first input signal to the positive signal integrator and the second input signal to the negative signal integrator during one time interval, and the periodic application of the first input signal to the negative signal integrator and the second input signal to the positive signal integrator during a second, subsequent, time interval of similar duration as the one time interval.

Electrical system with small signal suppression circuitry

Signals generated by a knock sensor are coupled to an electronic network for amplifying and processing the output signals of the knock sensor. The electronic network includes a device for charging a storage capacitor to a potential which is a function of the amplitude of the knock sensor output signal. The storage capacitor is coupled to the input of an amplifier via a normally closed first switch. A detector for sensing any disconnection of the knock sensor from the electronic system produces a control signal indicative of a disconnect condition. The control signal is used to open the normally closed first switch and to cause the input of the amplifier to be clamped to a reference potential which lies outside the signal range normally produced across the storage capacitor whereby the output of the output of the amplifier is placed at a predetermined level indicative of a disconnect condition. The amplifier thus produces signals at its output which are within a predetermined range during normal operation and a signal outside of this range in response to a knock sensor disconnect condition. Thus, a single line from the output amplifier carries regular normal signals and the disconnect signal lying outside the range of the normal signals.

Knock sensor system for detecting and responding to a disconnect

A comparator circuit has first and second inputs and an output and includes means for operating the comparator in alternate autozero and comparator phases. During an autozero phase, the inputs of the comparator are clamped to a reference potential and during a compare phase, input signals are applied to the input of the comparator. Control signals are applied to the inputs of the comparator during a portion of the compare phase. The control signals determine the state of the comparator output when the input signals applied to the inputs of the comparator are below a predetermined level.

Comparator with small signal suppression circuitry

A circuit for generating a bandgap voltage that is insensitive to temperature. The circuit includes an amplifier with a feedback loop having a high impedance output current mirror controlled by transistors connected to an output from the amplifier. The current mirror provides proportional currents to a pair of resistors that are connected to inputs to the amplifier, a first input receiving a temperature sensitive voltage from a first of the resistors, and a second input receiving a voltage that is a combination of a temperature sensitive voltage across a second of the resistors and a temperature sensitive offsetting voltage. The second resistor may be tapped to provide a selectable bandgap voltage. A reference voltage for operating the generator may be obtained from a voltage division of supply voltage by two resistors of the same type.

Temperature insensitive bandgap voltage generator tracking power supply

Two filter sections having different frequency responses are interconnected via selectively enabled switches, formed on the same integrated circuit (IC) as the filter sections, between a signal input terminal and a signal output terminal. The selectively enabled switches can be used to: (a) selectively connect the two filter sections in cascade between the signal input and output terminals to produce a bandpass filter; or (b) selectively connect the two filter sections in parallel to produce a notch filter, or (c) couple only one of the two filter sections between the signal input and output terminals; or (d) provide a short circuit between the signal input and output terminals. In a preferred embodiment the filter sections are switched capacitor filters. The filter system of the invention is highly suited for use in an engine knock signal processor integrated circuit.

Reconfigurable filter system

A telephone system coder/decoder (CODEC) having improved access for testing CODEC components and a method of testing a CODEC in which a test signal is not contaminated by passage through CODEC filters. Input test pads are positioned between the receive channel filters and the connection of the receive channel to the hybrid balance network, and an output test pad is positioned between the transmit channel filters and the connection of the transmit channel to the hybrid balance network. Test signals selectively applied to the test pads or to CODEC terminals indicate operation of receive programmable gain section, hybrid balance network frequency response, hybrid balance network echo cancellation, and the transmit buffer, buffer splitter and transmit programmable gain section in the transmit channel. The test signals do not go through the transmit and receive filters.

Testing circuit and method for a codec hybrid balance network

A differential, interpolating, switched capacitor filter and method of operation in which non-interpolating stages of the filter are clocked at a first frequency and a subsequent interpolating stage of the filter is operated at double the first frequency to achieve improved smoothing of the output wave form. The switched capacitors in the interpolating stage which feed forward a differential input from a prior stage to an input to the interpolating stage, and which feed a differential output from the interpolating stage back to an input thereto are paired and switches are provided for the added capacitors so that all of these capacitors are switched. Capacitors which are directly coupled to feed forward a differential input from a prior stage to the interpolating stage are also paired, but only the added capacitor is switched. Other directly coupled capacitors which feed back from the output of the interpolating stage to the input of prior stages are not paired, but are switched to prevent unwanted feedback of the interpolated output to the prior, non-interpolating, stages.

Differential interpolating switched capacitor filter and method

Methods of increasing the number of possible network configurations available during the manufacture of an integrated circuit hybrid balance network containing a fixed number of selectable network configurations in the manufactured network by including a network element selection layer programmable during the manufacturing process. The programming may be accomplished using ROM matrices programmed during or subsequent to the manufacturing process, or alternatively may be accomplished by the programming of the metal masks interconnecting the semiconductor portions of the IC without the necessity for changing the semiconductor masks.

Method of manufacturing a programmable hybrid balance network

An amplifier system embodying the invention includes an input stage comprising one or more differential amplifiers having a high degree of common mode rejection. The inputs of the differential amplifiers of the input stage are AC coupled to different signal input terminals which are adapted to receive small information signals riding on large common mode signals. The AC coupling blocks any dc level associated with the input signals from affecting the amplifier system and the high degree of common mode rejection maintains the gain of the amplifiers relatively constant over a wide range of common mode signals. The outputs of the differential amplifiers of the input stage are connected in common to an output node to sum their output signals and to reduce random noise associated with the input signals and the input stage. The output node of the input stage is AC coupled to the input of a second stage whose output is in turn AC coupled to a third output stage to reduce the effect of amplifier offsets. The gain of the amplifier system is controlled by low pass filters connected to the output node of the input stage and to the output of the second stage. In certain embodiments a biasing clock is coupled via resistors to the inputs of the differential amplifiers to generate a dc bias level at their inputs which is a function of the duty cycle of the clock, the resistor connected at the input and coupling capacitor connected to the input.

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Neshanic St., NJ, United States of America

Salomon Vulih