Micron Technology Incorporated

Koninklijke Philips Corporation N.v.

Aptina Imaging Corporation

Other

Lumileds LLC

Round Rock Research, LLC

Fairchild Semiconductor Corporation

Salman Akram

Warren M Farnworth

David R Hembree

Alan G Wood

James M Wark

Derek J Gochnour

Kyle K Kirby

William Mark Hiatt

Leonard Forbes

John O Jacobson

Michael E Hess

Sidney B Rigg

Charles Martin Watkins

Kie Y Ahn

Larry Duane Kinsman

Peter A Benson

C Patrick Doherty

David J Corisis

Jerry Michael Brooks

Syed Sajid Ahmad

Scott G Meikle

Eugene H Cloud

Andrew J Krivy

Mike Brooks

Akram Ditali

Steven David Oliver

Jorge L deVarona

Brent Keeth

Tongbi T Jiang

Mark E Tuttle

Yongjun Jeff Hu

Lu Velicky

Quanbo Zou

Mohamed A Ditali

Mike Hess

Joseph E Geusic

Jerome Chandra Bhat

J Michael Brooks

Daniel Alexander Steigerwald

Steven M McDonald

Paul D Shirley

William T Rericha

John R C Futrell

Charles L Turner

James M Shaffer

Alan E Laulusa

Troy A Manning

Todd A Merritt

Brian L Johnson

Shubneesh Batra

Chris G Martin

Ford B Grigg

Stefano Schiaffino

Alexander H Nickel

Michael D Chaine

Steven G Thummel

Steve Oliver

James P Chapman

Venkat Ananthan

Mark Hiatt

Jipu Lei

Eric J Smith

Jorge L De Varona

Mooi Guan Ng

Adam Manzonie

Tyler A Lowrey

Zhiqiang (Jeff) Wu

Grigoriy Basin

Daniel Cram

Jyoti Kiron Bhardwaj

Daniel A Koos

Jerome Chanra Bhat

Minh Ngoc Trieu

David R Hambree

Robert Blank

Alex Closson

Roy T Lange

Jérôme Chandra Bhat

A method according to embodiments of the invention includes providing a wafer of semiconductor devices grown on a growth substrate. The wafer of semiconductor devices has a first surface and a second surface opposite the first surface. The second surface is a surface of the growth substrate. The method further includes bonding the first surface to a first wafer and bonding the second surface to a second wafer. In some embodiments, the first and second wafer each have a different coefficient of thermal expansion than the growth substrate. In some embodiments, the second wafer may compensate for stress introduced to the wafer of semiconductor devices by the first wafer.

Method of bonding a semiconductor device to a support substrate

An elevated photosensor for image sensors and methods of forming the photosensor. The photosensor may have light sensors having indentation features including, but not limited to, v-shaped, u-shaped, or other shaped features. Light sensors having such an indentation feature can redirect incident light that is not absorbed by one portion of the photosensor to another portion of the photosensor for additional absorption. In addition, the elevated photosensors reduce the size of the pixel cells while reducing leakage, image lag, and barrier problems.

Elevated pocket pixels, imaging devices and systems including the same and method of forming the same

Light Emitting Devices (LEDs) are fabricated on a wafer substrate with one or more thick metal layers that provide structural support to each LED. The streets, or lanes, between individual LEDs do not include this metal, and the wafer can be easily sliced/diced into singulated self-supporting LEDs. Because these devices are self-supporting, a separate support submount is not required. Before singulation, further processes may be applied at the wafer-level; after singulation, these self-supporting LEDs may be picked and placed upon an intermediate substrate for further processing as required. In an embodiment of this invention, protective optical domes are formed over the light emitting devices at the wafer-level or while the light emitting devices are situated on the intermediate substrate.

Chip scale light emitting device package with dome

In one embodiment, a semiconductor device wafer () contains electrical components and has electrodes () on a first side of the device wafer (). A transparent carrier wafer () is bonded to the first side of the device wafer () using a bonding material () (e.g., a polymer or metal). The second side of the device wafer () is then processed, such as thinned, while the carrier wafer () provides mechanical support for the device wafer (). The carrier wafer () is then de-bonded from the device wafer () by passing a laser beam () through the carrier wafer (), the carrier wafer () being substantially transparent to the wavelength of the beam. The beam impinges on the bonding material (), which absorbs the beam's energy, to break the chemical bonds between the bonding material () and the carrier wafer (). The released carrier wafer () is then removed from the device wafer (), and the residual bonding material is cleaned from the device wafer ().

Laser de-bond carrier wafer from device wafer

In a general aspect, a power semiconductor device can include a silicon carbide (SiC) substrate and a SiC epitaxial layer disposed on the SiC substrate. The device can include a well region disposed in the epitaxial layer, a source region disposed in the well region and a gate trench disposed in the epitaxial layer and adjacent to the source region. The gate trench can have a depth that is greater than a depth of the well region and less than a depth of the epitaxial layer. The device can include a hybrid gate dielectric disposed on a sidewall of the gate trench and a bottom surface of the gate trench. The hybrid gate dielectric can include a first high-k material and a second high-k dielectric material that is different than the first high-k dielectric material. The device can include a conductive gate electrode disposed on the hybrid gate dielectric.

Hybrid gate dielectrics for semiconductor power devices

A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.

Semiconductor devices comprising nickel&#x2014; and copper&#x2014;containing interconnects

Semiconductor devices comprising nickel- and copper-containing interconnects

Semiconductor LED layers are epitaxially grown on a patterned surface of a sapphire substrate. The patterned surface improves light extraction. The LED layers include a p-type layer and an n-type layer. The LED layers are etched to expose the n-type layer. One or more first metal layers are patterned to electrically contact the p-type layer and the n-type layer to form a p-metal contact and an n-metal contact. A dielectric polymer stress-buffer layer is spin-coated over the first metal layers to form a substantially planar surface over the first metal layers. The stress-buffer layer has openings exposing the p-metal contact and the n-metal contact. Metal solder pads are formed over the stress-buffer layer and electrically contact the p-metal contact and the n-metal contact through the openings in the stress-buffer layer. The stress-buffer layer acts as a buffer to accommodate differences in CTEs of the solder pads and underlying layers.

LED with stress-buffer layer under metallization layer

In a general aspect, a power semiconductor device can include a silicon carbide (SiC) substrate and a SiC epi-layer disposed on the SiC substrate. The device can also include a first well region, a second well region disposed in the SiC epi-layer, a first source region disposed in the first well region, and a second source region disposed in the second well region. The device can further include a gate structure disposed on the SiC epi-layer and extending between the first source region and the second source region. The gate structure can include a hybrid gate dielectric. The hybrid gate dielectric can include a first high-k dielectric material and a second high-k dielectric material. The device can also include a conductive gate electrode disposed on the hybrid gate dielectric.

Methods and apparatuses for transferring heat from stacked microfeature devices are disclosed herein. In one embodiment, a microfeature device assembly comprises a support member having terminals and a first microelectronic die having first external contacts carried by the support member. The first external contacts are operatively coupled to the terminals on the support member. The assembly also includes a second microelectronic die having integrated circuitry and second external contacts electrically coupled to the first external contacts. The first die is between the support member and the second die. The assembly can further include a heat transfer unit between the first die and the second die. The heat transfer unit includes a first heat transfer portion, a second heat transfer portion, and a gap between the first and second heat transfer portions such that the first external contacts and the second external contacts are aligned with the gap.

Methods for transferring heat from stacked microfeature devices

A technique is disclosed for causing the top surfaces of solder bumps on a chip to be in the same plane to ensure a more reliable bond between the chip and a substrate. The chip is provided with solder pads that may have different heights. A dielectric layer is formed between the solder pads. A relatively thick metal layer is plated over the solder pads. The metal layer is planarized to cause the top surfaces of the metal layer portions over the solder pads to be in the same plane and above the dielectric layer. A substantially uniformly thin layer of solder is deposited over the planarized metal layer portions so that the top surfaces of the solder bumps are substantially in the same plane. The chip is then positioned over a substrate having corresponding metal pads, and the solder is reflowed or ultrasonically bonded to the substrate pads.

Reducing solder pad topology differences by planarization

Growing community of inventors

Boise, ID, United States of America

Salman Akram