Oracle International Corporation

Oracle America, Inc.

Motorola Corporation

Sun Microsystems, Inc.

Salim Chowdhury

David R Bearden

Georgios K Konstadinidis

Yu-Yen Mo

Akshay Sharma

Jingyan Zuo

Guo Yu

Techniques for circuit concurrent gate sizing and repeater insertion considering the issue of size conflicts are described herein. Certain of these techniques can be directed to coupled gates within levels of a levelized circuit falling within a coupling window defined by a minimum slack gate and adjacent gates coupled to the minimum slack gate with an adjacency parameter less than a predefined adjacency limit.

Methods and apparatus for repeater count reduction via concurrent gate sizing and repeater insertion

A system and method for topology construction for long and complex fan-out networks such as encountered in microprocessors include a modified Steiner tree algorithm with concurrent buffering to reduce post-buffer power/delay cost for a spanning tree. The system and method may prune Hanan points prior to calling a buffering tool to insert buffers and insert non-Hanan branching points. Embodiments may also include dividing a device into a plurality of super unit blocks, performing routing within each of the plurality of super units using a single crossing Steiner tree algorithm to determine a corresponding port, and aligning corresponding ports of each super unit to provide routing between the plurality of super units.

Concurrent timing-driven topology construction and buffering for VLSI routing

A processing device can identify gates of an integrated circuit design having a slack value less than a predefined slack threshold. The processing device can further, for each of the identified gates, determine (i) a number of nodes of the integrated circuit design that experience a timing slack improvement if the gate is swapped with an alternative implementation having a reduced delay or (ii) a sum of timing slack improvements experienced by nodes of the integrated circuit design if the gate is swapped with the alternative implementation having a reduced delay. The processing device can still further swap the gate with the alternative implementation having the reduced delay if the determined number or sum is greater than a corresponding predetermined threshold.

Gate substitution based system and method for integrated circuit power and timing optimization

A method for selecting gate sizes for a logic network of an integrated circuit, wherein the logic network is defined by a plurality of logic paths that includes nodes, gates and interconnect, includes assigning, at one or more computers, gate sizes to gates adjacent to timing path end nodes of the logic network, determining an n-tuple of performance/loading parameters for each of the assigned gate sizes based on gate and interconnect delay models, and determining whether two or more logic paths share a descendent gate. Two or more logic paths that share a descendent gate are coupled. The method also includes grouping the n-tuples of parameters of coupled logic paths into bins based on gate sizes of the shared descendent gate, recursively propagating, node by node, the bins of n-tuples of parameters along the coupled logic paths, detecting whether any of the bins of n-tuples of parameters are suboptimal for all of the coupled logic paths based on a comparison of the n-tuples of parameters in bin-pairs, and eliminating all n-tuples of parameters of the suboptimal bins along the coupled logic paths to prune gate sizes associated with the suboptimal bins.

Method and system for selecting gate sizes, repeater locations, and repeater sizes of an integrated circuit

For each of a plurality of interconnected gates forming one or more non-critical timing paths through a logic block, a gate size may be selected based on (i) a gate delay, (ii) a change in gate delay and gate power associated with downsizing the gate to a next available gate size, and (iii) signal arrival times at one or more inputs and outputs of the gate to minimize power consumed by the logic block while maintaining a specified cycle time.

System and method for selecting gates in a logic block

An improved, systematic approach is provided for automatically determining which cells in a circuit should be replaced to satisfy timing adjustment requirements (TAR's), and automatically replacing the cells with replacement cells to meet the TAR's. With the improved approach, there is a high likelihood that an optimal replacement scheme will be found which requires the fewest number of cells to be replaced while still satisfying all of the TAR's.

Systematic approach for performing cell replacement in a circuit to meet timing requirements

A method for inserting repeaters into an integrated circuit synthesis is provided. The method initiates with identifying possible repeater insertion locations along a signal routing pathway within an integrated circuit design. The possible repeater insertion locations are organized in a tree enabling bottom-up traversal. A set of solutions for each of the insertion locations is generated while traversing the tree in a first direction and the set of solutions is organized in a first and a second set, the first set ordered by a late mode capacitive load and the second set order by an early mode capacitive load. A computer readable medium including program instructions representing the method operations and a system are also included.

Repeater insertion for concurrent setup time and hold time violations

A method of inserting repeaters into a network to improve timing characteristics of the network. Extraction and timing tools provide an RC network description and a slack report describing electrical and timing characteristics of a network. The timing characteristics include required arrival times of a signal generated at a source to each of the sinks of the network. A maximum slew rate is also defined at each of the sinks. Initial candidate locations for insertion of repeaters is determined. For a given set of legal repeater sizes, one or more sets of midvalue repeater sizes are determined which are used in successive approximation to identify actual repeater sizes to be considered at each of the candidate locations. At each candidate location, capacitance, required arrival time, and slew rate value (c, q, s) are determined in a bottom-up procedure. Suboptimal and invalid (c, q, s) choices at each candidate location are eliminated during successive iterations of the bottom-up procedure until the source node is reached. Further, one or more of the candidate locations are also eliminated. When the source device is reached, the (c, q, s) values are determined at the source for the given size of the source. The particular combination of (c, q, s) values at the descendant nodes relative to the source that provide a maximum q value at the source are selected, and this procedure is repeated in a top-down traversal to identify the best solution for the net for the particular repeater sizes being used.

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Salim Chowdhury