Intel Corporation

Salim B Fedel

Mickey L Fandrich

Mamun Ur Rashid

Ranjeet Alexis

Thomas C Price

Virgil N Kynett

Richard J Durante

Geoffrey A Gould

Timothy Wade Goodell

Scott M Doyle

A flash memory device having a page buffer circuit with special testing modes. The page buffer circuit comprises a plane A and a plane B, each comprising a static random access memory array. The page buffer circuit further comprises a mode control circuit that maps the plane A and the plane B as a contiguous extended memory space accessible over a host bus. The page buffer circuit also maps the plane A and the plane B as a control store for a flash array controller of the flash memory device.

Special test modes for a page buffer shared resource in a memory device

A method and device for selectively enabling and disabling write access to flash blocks in a flash memory device. A lock command locks and unlocks a flash block in a flash array containing a plurality of flash blocks. A block data row decoder selects a block data area of the flash block, and a block status row decoder selects a block status area of the flash block. A lock bit in the block status area is programmed to a first logic state if the lock command specifies a lock flash block operation, or to a second logic state if the lock command specifies a release flash block operation. If a write protect input, read from the write protect pin of the flash memory device, indicates that a write lock is enabled and if a block enabled status bit in a block status register corresponding to the block indicates that the block has the write lock, then the lock bit is read and stored into the block enabled status bit in the block status register corresponding to the block. The write protect input is read again from the write protect pin and if the write protect input indicates that the write lock is enabled, and if the block enabled status bit in the block status register corresponding to the block, as updated, indicates that the block has the write lock, then an error is signaled.

Method and device for selectively locking write access to blocks in a

A nonvolatile memory comprises a memory array and a control circuit coupled to the memory array for performing memory operations with respect to the memory array. A storage circuit associated with the memory array is provided for storing a data. When the data is stored in the storage circuit, the memory array is locked from being accessed for the memory operations. A logic circuit is coupled to the control circuit and the storage circuit for preventing the control circuit from accessing the memory array with respect to the memory operations in accordance with the data. The logic circuit prevents the control circuit from accessing the memory array when the storage circuit stores the data. A control input is provided for receiving a control signal. The control signal is applied to the logic circuit and can be in a first voltage state and a second voltage state. When the control signal is in the first voltage state, the logic circuit is enabled to lock the memory array with respect to the memory operations in accordance with the data stored in the storage circuit. When the control signal is in the second voltage state, the logic circuit is disabled to lock the memory array and the memory array is allowed for the memory operations regardless of the data stored in the storage circuit.

Nonvolatile memory with blocks and circuitry for selectively protecting

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Folsom, CA, United States of America

Salim B Fedel