Xilinx, Inc.

Salim Abid

Victor Slonim

Parivallal Kannan

Jay T Young

Walter A Manaker, Jr

A method of assigning input/output (I/O) objects of a circuit design to banks of a target device using integer linear programming can include assigning the I/O objects of the circuit design to I/O groups according to compatibility among the I/O objects, and establishing a plurality of relationships, comprising measures of bank capacity, regulating assignment of the I/O objects of I/O groups to banks of the target device. Each measure of bank capacity can indicate a maximum number of I/O objects from a selected I/O group that can be assigned to a selected bank of the target device. The method also can include determining whether a feasible solution exists for assignment of the I/O objects of the circuit design to banks of the target device by minimizing an object function while observing the plurality of relationships.

Assignment of select I/O objects to banks with mixed capacities using integer linear programming

A method of assigning I/O objects to banks of a target device can include concurrently assigning I/O objects, including select I/O objects and clock I/O objects, of the circuit design to I/O groups according to an I/O standard associated with each I/O object. Each I/O group can include only I/O objects of a same I/O standard. The method also can include establishing a plurality of linear constraints for regulating assignment of the I/O groups to banks of the target device. The linear constraints can include range constraints indicating I/O banks capable of hosting clock I/O objects. The method also can include defining mutual relationships among selected ones of the linear constraints. An indication as to whether a feasible solution exists for assignment of the I/O groups to banks of the target device can be provided by minimizing a linear objective function while observing the linear constraints and the mutual relationships.

Simultaneous assignment of select I/O objects and clock I/O objects to banks using integer linear programming

A method of global clock placement for a circuit design to be implemented on a programmable logic device (PLD) can include identifying clock properties for the circuit design and identifying physical clock region attributes for the PLD. The method further can include specifying an Integer Linear Programming formulation (ILP) of a clock placement problem for the circuit design from the clock properties and the physical clock region attributes. The ILP formulation can be solved to determine whether a feasible clock placement exists for the circuit design.

Method of flexible clock placement for integrated circuit designs using integer linear programming

A method of input/output (I/O) assignment for a circuit design for a programmable logic device (PLD) can include determining I/O types for I/O objects specified by the circuit design, defining a plurality of virtual I/O bank-groups, wherein each virtual I/O bank-group includes at least one virtual I/O bank, and binding I/O objects of the circuit design into I/O groups according to the I/O types. A binary compatibility matrix can be created. The binary compatibility matrix can indicate the compatibility between the virtual I/O bank-groups and the I/O groups based upon the I/O types of I/O objects within each I/O group. A determination can be made as to whether a feasible solution exists for I/O assignment of the I/O objects of the circuit design according to a plurality of constraints and the binary compatibility matrix.

Assignment of I/O objects with multiple I/O standards to virtual I/O banks using integer linear programming

A method of physical design for a programmable logic device (PLD) can include associating movable objects of the PLD with a criticality measure that is dependent upon timing information for a configuration of the PLD (). The method further can include calculating the criticality measure for each movable object () and calculating a probability for each movable object (). The probability can depend upon the criticality measure for the movable object. The method also can include selecting one or more of the movable objects for controlled move generation within a simulated annealing process (). Movable objects are selected for controlled move generation according to the probabilities assigned to the movable objects.

Cost-independent criticality-based move selection for simulated annealing

A method of physical design for a programmable logic device can include associating target locations for movable objects with criticality measures and calculating the criticality measure for each target location. A probability for each target location can be calculated. The probability of the target location can be dependent upon the criticality measure for that target location. The method further can include selecting a target location for one of the movable objects for controlled movement during a simulated annealing process. The target location can be selected according to the probability corresponding to each target location.

Cost-independent critically-based target location selection for combinatorial optimization

Method and apparatus for phase-timing compensation is described. More particularly, a clock source and a clock sink of a path are identified for phase-timing compensation for a design. An absolute path slack is obtained, and phase offset of the clock source relative to the clock sink is determined. A normalizing factor responsive to the phase offset is generated. A normalized slack is computed using the absolute path slack and the normalizing factor.

Path slack phase adjustment

Method and code for dedicated resource placement enhancement is described. More particularly, a local area of a network is obtained for determining placement options of logic blocks to increase availability of dedicated resources within the local area. Each placement option is scored. This scoring may be based in part on whether a signal is to be propagated over a dedicated resource, and whether this signal is presently meeting a slack or target delay. Logic blocks, and therefore the dedicated resources, are placed after scoring.

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Lafayette, CO, United States of America

Salim Abid