Marvell Asia Pte., Ltd.

Adaptec, Inc.

Applied Micro Circuits Corporation

Qualcomm Incorporated

Marvellworld Trade Ltd.

Salil Suri

Scott Furey

Yingdong Li

Liping Guo

Michael J Moretti

David Geddes

Thomas Wu

Stillman F Gates

Chih-Lung Liu

Sassan Teymouri

Barry Allen Davis

Ramaswami Kishore

Taikhim Henry Tan

Kalyan Prabhu Gonar

Szu-Hsien Ho

John P Stubban

A switch device is configured to communicate with a plurality of hosts and a solid state drive (SSD). The plurality of hosts includes a first host and a second host. The switch device receives a first memory access command from the SSD, the first memory access command including an indication of the first host to indicate the first memory access command is intended for the first host. The switch device uses the indication of the first host in the first memory access command to route the first memory access command to the first host. The switch device removes the indication of the first host from the first memory access command prior to sending the first memory access command to the first host via a peripheral computer interface express (PCIe) interface of the switch device.

Switch device for interfacing multiple hosts to a solid state drive

In a system with multiple host computers and one or more single-port non-volatile memory devices, a non-volatile memory switch receives memory transaction messages from different root complexes corresponding to the multiple host computers. Each of at least some of the memory transaction messages includes a host identifier that identifies a root complex from which the memory transaction was received. The non-volatile memory switch generates modified memory transaction messages at least by changing host identifiers within memory transaction messages to a common value indicative of a single root complex to present to the one or more single-port non-volatile memory devices the different root complexes as the single root complex. The non-volatile memory switch maintains associations of memory transaction messages with corresponding ones of the different root complexes, and sends the modified memory transaction messages to the one or more single-port non-volatile memory devices.

Non-volatile memory switch with host isolation

The present disclosure describes apparatuses and methods for automatically mapping virtual functions to storage media to enable single root input output virtualization. A storage media switch manages access to virtual functions that execute behind a storage media interface managed by the switch. The switch includes a host interface through which the switch receives host commands. The switch determines virtual function identifiers associated with the host commands and automatically selects the virtual functions of the storage media based on the virtual function identifiers. The switch executes the host commands over the storage media interface using the virtual functions, and after execution, responds via the host interface to each of the host commands. By automatically mapping virtual functions in this way, the switch automatically enables single root input output virtualization of storage media, including storage media that is without native support for input output virtualization.

Enabling virtual functions on storage media

The present disclosure describes apparatuses and methods for virtualizing isolation areas of solid-state storage media. In some aspects, a storage media accelerator determines, via a storage media interface, a geometry of solid-state storage media. The accelerator selects, based on the geometry, an area of the solid-state storage media as an isolated unit of storage. A physical address of the isolated unit of storage is then mapped to a virtual address. The accelerator exposes, via the virtual address, the isolated unit of storage through a host interface to enable host access of the isolated unit of storage. The accelerator may also remap the isolated unit of storage to other areas of the solid-state storage media without host interaction. By so doing, the accelerator may provide virtualized isolation and partitioning functionalities to a host, while efficiently handling lower-level storage media functions, such as wear leveling and load balancing, without host involvement.

Virtualizing isolation areas of solid-state storage media

A NVM switch has been designed that allows multiple hosts to simultaneously and independently access a single port NVM device. While this active-active multi-host usage configuration allows for a variety of uses of lower cost single port NVM device, an issue with one of the hosts can delay or block transactions between the other host and the NVM device. The NVM switch includes logic that isolates activity of the multiple hosts despite logic of the switch being shared across the hosts. When the switch detects an issue with one host ('error host'), the switch clears the in-flight commands of the error host and flushes data of the error host. Likewise, the NVM switch ensure proper communication of error reporting from attached NVM devices to the multiple hosts.

A non-volatile memory express (NVMe) switch is located in between a host and storage. A first storage access command is received from a host via a peripheral computer interface express (PCIe) interface to access the storage. The first storage access command conforms to NVMe and the storage comprises two or more solid-state drives (SSDs). A respective second storage access command is sent to the two or more SSDs based on the first storage access command. A respective completion is received from each of the two or more SSDs based on the respective second storage access command. A completion is sent to the host via the PCIe interface based on the received completions from each of the two or more SSDs.

Managed switching between one or more hosts and solid state drives (SSDs) based on the NVMe protocol to provide host storage services

The present disclosure describes aspects for providing Quality of Service (QoS) over a virtual interface for solid-state storage. In some aspects, a storage media switch receives, from a host device, an input/output (I/O) command for data access including an identifier for a virtual interface associated with a namespace through which solid-state storage is accessible. The switch determines an amount of the data that the I/O command will access through the namespace. A determination is made whether the amount of data that the I/O command will access through the namespace exceeds a predefined threshold for data access through that namespace. In response to determining that the amount of data does not exceed the predefined threshold, the I/O command is released to the solid-state storage to enable the data access. By so doing, the switch may provide QoS for the virtually accessed solid-state storage based on an access parameter of the namespace.

Apparatus and methods for providing quality of service over a virtual interface for solid-state storage

A first command is received from a virtual or physical host associated with a storage system which includes two or more hosts. The first command comprises one or more physical request page (PRP) entries associated with the non-volatile memory express (NVMe) standard. The one or more PRP entries are modified with an indication of the virtual or physical host. A second command is sent with the modified one or more PRP entries to a solid state drive (SSD). A memory request is received from the SSD, where the memory request comprises the modified one or more PRP entries. The memory request is routed to the virtual or physical host based on the indication of the virtual or physical host in the modified one or more PRP entries.

Modifying NVMe physical region page list pointers and data pointers to facilitate routing of PCIe memory requests

A method and apparatus for bridging network protocols is disclosed. In one embodiment, a data frame is received and stored in a dual-port memory queue by hardware logic. An embedded processor is notified of the data frame once a programmable number of bytes of the data frame have been received and stored. Once notified, the embedded processor may then undertake to read the data frame from the memory queue while the hardware logic is still writing to the memory queue. In one embodiment, the processor may then translate the data frame's protocol and begin transmitting it out over a network connection, all while the data frame's payload is still being received.

Data frame processing

Methods and apparatus for bridging network protocols are disclosed. A protocol bridge may be used to function as a target for a network processor while performing a target mode operation, while functioning as an initiator on behalf of the network processor while performing an initiator mode operation. In one embodiment, the protocol bridge determines the mode of operation based on information in a received frame's header. In another embodiment, the protocol bridge couples a Fiber Channel device to a storage processor on a packet-over-SONET network.

Method for bridging network protocols

Method and apparatus for implementing a data frame processing model

Methods and apparatus for bridging network protocols are disclosed. A protocol bridge may be used to function as a target for a network processor while performing a target mode operation, while functioning as an initiator on behalf of the network processor while performing an initiator mode operation. In one embodiment, the protocol bridge determines the mode of operation based on information in a received frame's header. In another embodiment, the protocol bridge couples a Fibre Channel device to a storage processor on a packet-over-SONET network.

Growing community of inventors

Fremont, CA, United States of America

Salil Suri