Xilinx, Inc.

Monterey Design Systems, Inc.

Synopsys, Inc.

Salil Ravindra Raje

David A Knol

Lawrence Thomas Pileggi

Majid Sarrafzadeh

Douglas B Boyle

Sharad Malik

Gary K Yeap

Feroze P Taraporevala

Abhijeet Chakraborty

Abhishek Ranjan

Lilly Shieh

Dennis Yamamoto

Dinesh D Gaitonde

Christopher J Dunn

Robert E Shortt

Tong Gao

Padmini Gopalakrishnan

James S Koford

Nabeel Shirazi

Sonal Santan

Stephen P Rozum

Sudipto Chakraborty

Suman Kumar Timmireddy

Yong Li

Fernando J Martinez Vallina

Heera Nand

David Gluss

Susheel Kumar Puthana

Joseph T Rahmeh

Satyamurthy Pullela

Eric McCaughrin

Emre Tuncer

Sam Jung Kim

Archie Li

Yau-Tsun Steven Li

Satamurthy Pullela

Ethan T Parker

Jackson David Kreiter

Olivier R Coudert

Implementing hardware accelerators using programmable integrated circuits may include performing, using a processor, a design flow on a static circuit design. The static circuit design may specify a region reserved for a hardware accelerator and a static region comprising interface circuitry configured to couple the hardware accelerator with an external node. The design flow may generate an implemented static circuit design. Metadata describing the interface circuitry may be generated using a processor. A device support archive including the implemented static circuit design and the metadata may be written, using the processor, to a computer readable storage medium.

Hardware acceleration device handoff for using programmable integrated circuits as hardware accelerators

A computer-implemented method of converting a circuit design for a programmable logic device (PLD) to a standard cell circuit design can include unmapping a PLD circuit design to a gate level netlist, mapping logic gates of the netlist to functionally equivalent standard cells, and including the standard cells within the standard cell circuit design. Design constraints for the standard cell circuit design can be automatically generated. The design constraints for the standard cell circuit design can be output.

Creating a standard cell circuit design from a programmable logic device circuit design

A method of partitioning a design across a plurality of integrated circuits can include creating a software construct for each one of the plurality of integrated circuits and assigning a plurality of instances to a selected software construct. Each of the plurality of instances can be from a different logic hierarchy. The method further can include automatically adding at least one input/output buffer and port to the selected software construct to accommodate the plurality of instances and creating nets connecting the plurality of instances and the at least one input/output buffer and port within the selected software construct.

Partitioning a large design across multiple devices

A computer-implemented method of placing input/output (I/O) pins of a circuit design for an integrated circuit (IC) can include selecting a bus from a plurality of buses, where the selected bus includes a plurality of I/O pins and is part of an interface, and, for each of a plurality of banks of the IC, determining a cost of assigning the selected bus to the bank according, at least in part, to a measure of proximity of the bank to another bank including a bus of the interface. The method can include selecting an available bank having a lowest cost, assigning at least one of the plurality of I/O pins of the selected bus not assigned to a bank of the IC to the selected bank, and outputting a circuit design including an association of I/O pin(s) of the selected bus to the selected bank.

Automatic pin placement for integrated circuits to aid circuit board design

A method is provided for generating an implementation of an electronic design. Information describing a set of strategies is specified. Each strategy of the set includes one or more options for directing the generation of an implementation of the electronic design, with each option being a set of one or more input parameter values to an implementation tool. The set of strategies is displayed and a subset of the set of strategies is selected in response to user input. For each strategy of the subset, a respective implementation of the electronic design is generated from a specification of the electronic design in a hardware description language. The option or options of each strategy are input to one or more implementation tools to direct the generation of the respective implementation for the strategy. For each strategy of the subset, quality metrics are displayed for the respective implementation of the electronic design.

Strategies for generating an implementation of an electronic design

A method of performing timing analysis on a circuit design for an integrated circuit (IC) can include selecting a physical portion of the IC that includes at least one instance of a logic hierarchy and generating a local timing constraint specific to the physical portion. The method also can include creating a software representation of the physical portion of the IC. The software representation can specify the local timing constraint and a shell netlist for the physical portion. The method further can include performing a timing analysis upon, at least part of, the circuit design using the software representation.

Method of memory and run-time efficient hierarchical timing analysis in programmable logic devices

A floor planner tool for integrated circuit design which provides tools and displays for a designer to create a floor plan to define desired placement of circuits defined in a logical netlist by creating a physical hierarchy comprised of nested pblocks. Each pblock is a data structure which contains data which defines which circuits from the logical netlist are assigned to it. Each pblock stands alone and can be input to a place and route tool without the rest of the physical hierarchy. Each pblock data structure contains pointers to the circuits on the netlist assigned to that plbock, identifies other pblocks nested within it and contains a list of pins for the instances within the pblock. Net data structures in the physical hierarchy define which nets are connected to which pins.

System for representing the logical and physical information of an integrated circuit

A floor planner tool for integrated circuit design which provides tools and displays for a designer to create a floor plan to define desired placement of circuits defined in a logical netlist by creating a physical hierarchy comprised of nested pblocks. Each pblock is a data structure which contains data which defines which circuits from the logical netlist are assigned to it. Each pblock stands alone and can be input to a place and route tool without the rest of the physical hierarchy. Each pblock data structure contains pointers to the circuits on the netlist assigned to that plbock, identifies other pblocks nested within it and contains at least a list of boundary pins for that pblock. Net data structures in the physical hierarchy define which nets are connected to which pins. PCellview data structures define the internal structure of each pblock.

Data structures for representing the logical and physical information of an integrated circuit

A floor planner tool for integrated circuit design which provides tools and displays for a designer to create a floor plan to define desired placement of circuits defined in a logical netlist by creating a physical hierarchy comprised of nested pblocks. Each pblock is a data structure which contains data which defines which circuits from the logical netlist are assigned to it. Each pblock stands alone and can be input to a place and route tool without the rest of the physical hierarchy. Each pblock data structure contains pointers to the circuits on the netlist assigned to that plbock, identifies other pblocks nested within it and contains at least a list of boundary pins for that pblock.

Process for adjusting data structures of a floorplan upon changes occurring

System for creating a physical hierarchy of a chip without restriction by invading a logical hierarchy of logic blocks

A floor planner tool for integrated circuit design which provides tools and displays for a designer to create a floor plan to define desired placement of circuits defined in a logical netlist by creating a physical hierarchy comprised of nested physical blocks (pblocks). Each pblock is a data structure which contains data which defines which circuits from the logical netlist are assigned to it. Each pblock stands alone and can be input to a place and route tool without the rest of the physical hierarchy. Each pblock data structure contains pointers to the circuits on the netlist assigned to that pblock, identifies other pblocks nested within it and contains a list of pins for the instances within the pblock. Net data structures in the physical hierarchy define which nets are connected to which pins.

The present invention, generally speaking, provides a placement method for the physical design of integrated circuits in which natural topological feature clusters (topo-clusters) are discovered and exploited during the placement process. Topo-clusters may be formed based on various criteria including, for example, functional similarity, proximity (in terms of number of nets), and genus. Genus refers to a representation of a netlist in terms of a number of planar netlists&#x2014;netlists in which no crossing of nets occurs. Topo-clusters drive initial placement, with all of the gates of a topo-cluster being placed initially in a single bin of the placement layout or within a group of positionally-related bins. The portion of a topo-cluster placed within a given bin is called a quanto-cluster. An iterative placement refinement process then follows, using a technique referred to herein as Geometrically-Bounded FM (GBFM), and in particular Dual GBFM. In GBFM, FM is applied on a local basis to windows encompassing some number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region does not participate. The cost function takes account of actual physical metrics&#x2014;delay, area, congestion, power, etc. 'Dual' refers to the fact that each iteration has two phases. During a first phase, FM is performed within a region on a quanto-cluster basis. During a second phase, FM is performed within the region on a gate basis. GBFM occurs in the context of recursive quadrisection. Hence, after GBFM has been completed, a further quadrisection step is performed in which each bin is divided into four bins, with a quarter of the gates of the original bin being placed in the center of each of the resulting bins. GBFM then follows, and the cycle repeats until each bin contains a fairly small number of gates. Following the foregoing global placement process, the circuit is then ready for detailed placement in which cells are assigned to placement rows.

Placement method for integrated circuit design using topo-clustering

The present invention, generally speaking, provides a placement method for the physical design of integrated circuits in which natural topological feature clusters (topo-clusters) are discovered and exploited during the placement process. Initial placement and placement refinement may be performed hierarchically using topocluster trees. A topocluster tree may be used to drive initial placement. An iterative placement refinement process then follows, using a technique referred to herein as Geometrically-Bounded FM (GBFM). In GBFM, FM is applied on a local basis to windows encompassing some number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region does not participate. The cost function takes account of actual physical metrics-delay, area, congestion, power, etc. During placement refinement using GBFM, cluster size is adjusted iteratively from large to small as determined by horizontal cuts within the topocluster tree. GBFM occurs in the context of recursive quadrisection. Hence, after GBFM has been completed, a further quadrisection step is performed in which each bin is divided into four bins, with a quarter of the gates of the original bin being placed in the center of each of the resulting bins. GBFM then follows, and the cycle repeats until each bin contains a fairly small number of gates. Topocluster trees may also be used for quadrisection. Following the foregoing global placement process, the circuit is then ready for detailed placement in which cells are assigned to placement rows.

Methods and apparatus for a physical &ldquo;sign-off&rdquo; prototype tool that includes a prototype tool that generates a physical prototype for a design and a optimization tool that provides a designer with the option to further optimize the physical prototype before signing off on the design. In either situation, the &ldquo;sign-off&rdquo; prototype provides a forward prediction of the area, timing and performance of the final GDS of the design generated by a physical implementation tool.

Method and apparatus for generating sign-off prototypes for the design and fabrication of integrated circuits

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San Jose, CA, United States of America

Salil Ravindra Raje