Synopsys, Inc.

Salem Lee Ganzhorn

Donald John Oriordan

Jonathan Lee Sanders

Friedrich Gunter Kurt Sendig

Barry Andrew Giffel

Hsiang-Wen Jimmy Lin

Kristin M Beggs

Govindaswamy Chithamudali

Yevgenia Murad Beglaryan

Liana Badalyan

Systems and method for generating graphical visualizations of an integrated circuit (IC) design may comprise configurations for generating interactive graphical visualizations of the IC design configured for providing informative overlays to the graphical visualizations based on a selected zoom level of the graphical visualization. In certain embodiments, the graphical overlays may be generated over corresponding objects for providing information regarding hierarchies of objects, or for generating perceptible overlays over objects regardless of a zoom level of the interactive graphical visualization.

Hierarchical dynamic heat maps in full custom EDA applications

Embodiments relate to designing of integrated circuits using generation and instantiation of circuit stencils. The circuit stencil represents an abstracted version of the circuit segment. The circuit stencils include collapsed versions of the connectivity information of components and nodes of the integrated circuit. The collapsed version of the connectivity information is generated by analyzing functionality of the circuit segment and removing or replacing at least one redundant component or node of the circuit segment without modifying the functionality. The circuit stencil is used for instantiating or referencing components into a second integrated circuit.

Integrated circuit design using generation and instantiation of circuit stencils

Embodiments relate to schematic overlays describing modification to a base design for exploring modification or verification of the base design. Test circuitry may be modified or inserted without effecting the change in a base design schematics. The modifications to the base design schematics are also highlighted in views at a level of hierarchy where the modifications were made as well as at a higher levels of circuit abstraction. By using schematic overlays, modification to the base design can be avoided while creating a testbench.

Schematic overlay for design and verification

A bi-directional EDA-browser bridge mechanism enables an EDA system and its related (external) tools to interact with a browser. The EDA-browser bridge uses a design markup language (DML) to communicate with the browser, using a document-based approach rather than a more traditional programming/API-based approach to extending (e.g., integrating tools) the EDA system. By using a markup language, extending the EDA system becomes more accessible to a wider community of developers (e.g., those with web development skills, as opposed to those with just EDA programming skills), and be able to leverage a wider variety of powerful third-party libraries, such as jQuery or D3. For example, developers are able to more easily generate interactive interfaces for viewing results related to the EDA system.

Scheme and design markup language for interoperability of electronic design application tool and browser

Some embodiments provide a system that performs a simulation within an electronic design automation (EDA) application. During operation, the system obtains a design from a user of the EDA application. Next, the system performs the simulation using the design to create a set of current simulation results associated with the design. The system then automatically saves a current design state of the design which is associated with the current simulation results. Finally, the system enables subsequent access to the current design state and one or more previous design states of the design by the user through a graphical user interface (GUI) associated with the EDA application.

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Apex, NC, United States of America

Salem Lee Ganzhorn