Freescale Semiconductor,inc.

Salem Boudjelel

Eric Pierre Rolland

Bernard Pechaud

An integrated circuit device comprises at least one clock monitor. The at least one clock monitor comprises a timer arranged to receive a clock signal, generate a first timing signal arranged to toggle between states in response to a trigger edge of the clock signal, and generate a second timing signal arranged to toggle between states in response to a trigger edge of the clock signal such that a state transition of the second timing signal in response to a trigger edge of the clock signal is delayed by a period T with respect to the trigger edge of the clock signal in response to which that transition occurs. The at least one clock monitor further comprises a detector arranged to receive at a first input thereof the first timing signal, receive at a second input thereof the second timing signal, compare states of the first and second timing signals, and configure an indication of a timing discrepancy based at least partly on the comparison of the first and second timing signals.

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Daux, France

Salem Boudjelel