Intel Corporation

Saleem Mohammadali

Bapiraju Vinnakota

Carl A Alberola

Corey Gee

David W Gilbert

Bapiraiu Vinnnakota

New instruction definitions for a packet add (PADD) operation and for a single instruction multiple add (SMAD) operation are disclosed. In addition, a new dedicated PADD logic device that performs the PADD operation in about one to two processor clock cycles is disclosed. Also, a new dedicated SMAD logic device that performs a single instruction multiple data add (SMAD) operation in about one to two clock cycles is disclosed.

Single instruction multiple data add processors, methods, systems, and instructions

Data packet arithmetic logic devices and methods

A buffer having an associated state array to store the current state of the buffer. The state array includes a bit array having a number of entries, each of the entries including a status bit to indicate storage of a corresponding packet in the buffer.

State-based jitter buffer and method of operation

According to one embodiment of the invention, an apparatus is provided which includes a first register to hold an initial value of a first index associated with a looping instruction to be executed for a number of iterations, a second register to hold an initial value of a second index associated with the respective looping instruction, and a third register to hold data indicating non-linear variation pattern associated with the second index. For each iteration, actual increment of the first index and actual increment of the second index are set based on a target increment and the data indicating the non-linear variation pattern associated with the second index.

Growing community of inventors

Karnataka, India

Saleem Mohammadali