Baysand Inc.

Salah M Werfelli

Jonathan C Park

Yin Hao Liew

Kok Seong Lee

Kok Siong Tee

Jonathan C Parks

Jeremy Jia Jian Lee

WeiZhi Kang

Wan Tat Hooi

Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. In other aspects, ESD circuitry is provided at corners of the IC layout and optionally within selected I/O slots. Decap circuitry is provided at an outer edge of the IC layout and is scalable in order to meet different requirements.

Flexible, space-efficient I/O circuitry for integrated circuits

Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD protection circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from power supply requirements of signal I/O buffers of another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. Customization circuitry also provides for flexible pad options, whereby the IC pads may be configured for different packaging technology, for example, for wire bonding for flip-chip bonding, or for other types of bonding.

An integrated circuit includes a gate array layer having a two-dimensional array of logic gates, each logic gate including multiple transistors. At least one upper template-based metal layer is coupled to the gate array layer and is configured to define at least one of a power distribution network, a clock network and a global signal network. A configuration of traces of the upper template-based metal layer is at least mainly predetermined prior to design of the integrated circuit.

Gate array architecture with multiple programmable regions

Systems and methods are disclosed for forming a custom integrated circuit (IC) with a first fixed (non-programmable) region on a wafer with non-customizable mask layers, wherein the first fixed region includes multiplicities of transistors and a first interconnect layer and a second interconnect layer above the first interconnect layer which form base cells; and a programmable region above the first fixed region with customizable mask layers, wherein at least one mask layer in the programmable region is coupled to the second interconnect layer which provides electrical access to all transistor nodes of the base cells and wherein the programmable region comprises a third interconnect layer coupled to the customizable mask layers to customize the IC. A second fixed region may be formed above the programmable region to provide multiple fixed regions and reduce the number of required masks in customizing the custom IC.

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Morgan Hill, CA, United States of America

Salah M Werfelli