Kabushiki Kaisha Toshiba

Saku Hashiura

Takeshi Sonehara

Takeshi Murata

Fumiki Aiso

Junya Fujita

According to one embodiment, a plurality of memory cell transistors including a floating gate and a control gate and a plurality of peripheral circuit transistors including a lower electrode portion and an upper electrode portion are included. The floating gate includes a first polysilicon region, and the lower electrode includes a second polysilicon region. The first polysilicon region is a p-type semiconductor in which boron is doped, and the second polysilicon region is an n-type semiconductor in which phosphorus and boron are doped.

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Mie, Japan

Saku Hashiura