Hitachi, Ltd.

Sakou Ishikawa

Tatsuya Sakai

Yutaka Watanabe

Kenichi Kurosawa

Michio Morioka

Tetsuaki Nakamikawa

Shin Kokura

Katsuro Wakai

A computer memory system is disclosed with an input/output circuitry capable of separating the load separating the load capacitance of an output circuit of a semiconductor memory connected to a memory bus from the memory bus. In order to separate the load capacitance of a semiconductor memory connected to a memory bus signal line, a Schottky diode is arranged between the semiconductor memory and the memory bus line, and a voltage control circuit is provided to control whether a reverse bias voltage is applied to the Schottky diode. The speed of signal transmission does not decrease even when a large number of semiconductor memories are connected to the memory bus since the load capacitance of the semiconductor memories is separated from the bus. Therefore, it is possible to construct a high speed and large capacity memory system.

Memory system using schottky diodes to reduce load capacitance

In a data processing unit having an instruction precontrol function, when an instruction for new address mode setting, branch address generation and branching is decoded in a preexecution cycle of the instruction, a branch destination address is calculated by using an address mode of the branch destination address represented by a specific bit in operand data of the instruction, as the address mode, and the branch destination instruction is fetched based on the calculated address.

System for calculating branch destination address based upon address

A high-speed dividing apparatus includes first and second carry-save adders and a half carry-save adder and the outputs of the first carry-save adder are connected to the inputs of the second carry-save adder and half carry-save adder. The first carry-save adder is capable of carrying out either the addition or the subtraction of the divisor. The second carry-save adder is adapted to carry out the subtraction of a divisor, and the half carry-save adder the addition thereof. The first and second carry-save adders generate half-sums and half-carries, and the half carry-save adder generates a half-carry. A half-sum of the divisor addition is obtained by inverting the half-sum of the second carry-save adder by an inverter. A pair of half-sum and half-carry is supplied to each of carry look-ahead logics. A carry look-ahead logic is connected to each adder. A quotient determining logic is adapted to determine quotient bits in response to outputs from carry-save adder and half carry-save adder and carry look-ahead logics. A selector control logic controls a selector in accordance with the quotient such that one of the pairs of the half-sums and half-carries of the divisor addition and divisor subtraction, and either the divisor or its inversion are supplied to the first carry-save adder. An arbitrary number of stages can be arranged in a binary tree configuration in the same manner.

Carry-save-adder three binary dividing apparatus

A high-speed dividing apparatus includes a first, second and third carry save adders (CSA's) and the outputs of the first CSA are connected to the inputs of the second and third CSA's. The first CSA is capable of carrying out either the addition or the subtraction of a divisor. The second CSA is adapted to carry out the subtraction of a divisor, and the third CSA the addition thereof. A carry look-ahead logic is connected to each CSA. A quotient determining logic is adapted to determine quotient bits in response to outputs from CSA's and carry look-ahead logics. A selector control logic is adapted to control selectors in response to quotient bits so that outputs from one of the second and third CSA's and either a divisor or the complement thereof are selectively supplied to the inputs of the first CSA. An arbitrary number of stages can be arranged in a binary tree configuration in the same manner.

Dividing apparatus

In a system which employs SEC-DED codes constituted by data bits added to redundant bits and is capable of detecting and correcting a single bit error while detecting a double or more bit error, detection is made on miscorrection ascribable to a triple bit error. When a single bit error is detected by an error detecting and correcting circuit in the SEC-DED code read out from a memory, all the corrected data bits are inverted in state and rewritten in the memory after having been added to new redundant bits. Subsequently, the data bits together with the redundant bits are read out from the memory and supplied to the error detecting and correcting circuit. The data bits obtained from the error detecting and correcting circuit are compared with the corrected and inverted data bits available before being written in the memory, to thereby determine the presence of an error encompassing more than (m+1) bits on the basis of the result of comparison.

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Hadano, Japan

Sakou Ishikawa