Lsi Logic Corporation

Lsi Corporation

Saket K Goyal

Thai Minh Nguyen

Arun K Gunda

Prasad Subbarao

Manjunatha Gowda

Santhanakrishnan Raman

Prabhakaran Krishnamurthy

Hunaid Hussain

Narendra B Devta Prasanna

James Ngo

Vankat Rajesh Atluri

An apparatus having a core and one or more logic blocks is disclosed. The core may be embedded within the apparatus. The core is generally (i) configured to perform a function and (ii) wrapped internally by a first scan chain before being embedded within the apparatus. The logic blocks may be (i) positioned external to the core and (ii) coupled to one or more parallel interfaces of the first scan chain. A second scan chain may be configured to wrap both the logic blocks and the core.

Core wrapping in the presence of an embedded wrapped core

A test system tests a circuit. Compressed scan data subsets are stored, one at a time, in a memory of the test system. The multiple compressed scan data subsets correspond with multiple scan chains in a function block of the tested circuit. Transmission of the compressed scan data subset from the memory to the tested circuit is controlled by the test system. The test system receives a compacted test output subset from the tested circuit and provides a test system output that indicates a presence of any errors in functioning of the tested circuit.

Testing a circuit with compressed scan chain subsets

A method and system is provided for creating a tap controller in a slice for use during custom instance creation to avoid the need of a boundary scan synthesis tool. Aspects of the present invention include during slice creation, using a software tool to create a test access port (TAP) from slice resources; during instance creation, allowing a customer to design a custom chip using the software tool to select which structures to use on the slice; and based on the customer selections, reconfiguring at the instance level connections between the tap controller and the selected structures.

Method for creating a JTAG tap controller in a slice for use during custom instance creation to avoid the need of a boundary scan synthesis tool

A library useable to facilitate testing of IO cells of an ASIC. The library includes IO cell identifications and test structures associated with the IO cell identifications, and identifies which test structures are required to test which IO cells. Preferably, the library forms part of an ASIC design system. A method of testing IO cells of an ASIC is also provided, and includes using the library to determine which test structures to use to test the IO cells, and testing the IO cells using the test structures.

Extensible IO testing implementation

A method and system is provided for handling unused structures in a slice during custom instance creation to avoid the need of a boundary scan synthesis tool, wherein the slice includes an embedded boundary scan chain having a particular length and order. Aspects of the present invention include using a software tool during slice creation to create at least one slice connectivity file. During instance creation, a customer designs a custom chip using the software tool by selecting which structures are to be use on the slice. The slice connectivity file is then reused for the instance by reading the connectivity file to determine which structures in the file are used and not used based on the customer's selections. Thereafter, the slice is reconfigured to include dummy logic in unused structures, such that the boundary scan chain retains the same length and order.

Handling of unused coreware with embedded boundary scan chains to avoid the need of a boundary scan synthesis tool during custom instance creation

The present invention provides a method and a system of generic implementation of sharing test pins with I/O cells. The method includes a step of making a general change in a testlib file. The testlib file is suitable for controlling I/O cell pins to gain test access. The general change restricts I/O cells for sharing with test pins. The method further includes a step of making iogen changes for sharing. Optionally, the method may include a step of making a cell level change in the testlib file. The cell level change overrides restrictions defined by the general change.

Method and system of generic implementation of sharing test pins with I/O cells

A library to be used in an ASIC design system includes information to be used for verification of test structures. The library includes information regarding the ability to combine test pins for verification of the test structure and information regarding the sharing of ports for verification of the test structure. A user of the ASIC design system can include custom test structures in the library for verification.

Flexible and extensible implementation of sharing test pins in ASIC

A method and system for predicting delay of a multi-million gate sub-micron ASIC design is disclosed. The method and system include automatically partitioning a netlist into at least two logic cones, and running respective instances of a delay prediction application on the logic cones on at least two computers in parallel.

Growing community of inventors

San Jose, CA, United States of America

Saket K Goyal