Seikosha Co., Ltd.

Nippon Precision Circuits Inc.

Sony Corporation

Kyocera Corporation

The University of Tokyo

Other

Sakae Tanaka

Yoshiaki Watanabe

Yoshihisa Ogiwara

Katsuo Shirai

Shingo Takahashi

Hiroki Sato

Masato Hatanaka

Tomoaki Takahashi

Tadahiko Yamaoka

Kenichi Watanabe

Masayuki Kyomoto

Toru Moro

Noboru Motai

Toshio Ohhoshi

Shintaro Honda

Kazuya Umeyama

Akio Ohkoshi

Masahiko Hashida

Takao Nakano

Ikufumi Yamada

Takashi Sasaki

Yaeko Suzuki

Takehiro Matsubara

Keiko Shibuki

Kazunori Saito

Toshio Kashiwa

Toshio Ohboshi

Seiji Sanada

A prediction device includes a first prediction unit that outputs first prediction information regarding a joint at a second point in time after a predetermined period of time from a first point in time, from a medical image showing the joint of a subject at the first point in time. The first prediction unit includes a first prediction model capable of estimating the first prediction information from the medical image.

Prediction device, prediction system, control method, and control program

An estimation apparatus includes an input unit and an approximator. Input information including an image in which a bone appears is input into the input unit. The approximator is configured to determine an estimation result related to bone density of the bone from the input information. The approximator includes a learned parameter to obtain the estimation result.

Estimation apparatus, estimation system, and computer-readable non-transitory medium storing estimation program

A bone fracture internal fixator for repairing a bone fracture of a femoral neck that allows load to be applied to the associated bone parts evenly, and increases the connecting strength between the femoral head and femoral shaft while minimizing the risk of the femoral head being torn apart by the inner connecting member by increasing the diameter of the inner fixing member. The central axial line of the femoral head is offset from the central axial line of the intramedullary nail placed in the medullary cavity of the femoral shaft. In order to bring the inner fixing member such as a lag screw configured to be inserted through the femoral neck close to the central axial line of the femoral neck, the central axial line of the through hole for receiving the inner fixing member is offset from the central axial line of the intramedullary nail.

Internal fixator for bone fracture

A method of driving an active matrix type liquid crystal display unit of the type including a plurality of liquid crystal layers, a plurality of switching elements, a plurality of pixel electrodes each connected between a liquid crystal layer and a switching element, a common electrode connected to the liquid crystal layers, a plurality of stick capacitive elements each connected to a pixel electrode, and a plurality of scanning lines each connected to a switching element, the method including the steps of selectively turning on the switching elements by applying selection signals to the scanning signal lines of the active matrix type liquid crystal display unit; supplying picture signals to picture signal lines connected with the pixel electrodes through the switching elements; and providing an alternating voltage as an integral fraction of a horizontal interval of a picture frame as at least a common voltage at the common electrode and/or a stick capacitor voltage supplied to the capacitive elements, so as to provide that the ratio of the change in liquid crystal light transmittance T to the change in picture signal voltage V.sub.SIG is smaller than the ratio of the change in liquid crystal light transmittance T to the change in effective voltage applied to a respective liquid crystal layer.

Method for improving the gradational display of an active type liquid

A silicon thin film transistor array includes a plurality of silicon thin film transistors in an array-like form, each silicon thin film transistor including an insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating layer formed on the insulating substrate containing the gate electrode, a pair of first impurity contained silicon layers formed on the gate insulating layer in such a manner as to transversely cross a terminal part of the gate electrode, an intrinsic silicon layer formed on the pair of first impurity contained silicon layers and on the gate insulating layer between the pair of first impurity contained silicon layers in such a manner as to connect the pair of first impurity contained silicon layers, a protective insulation layer formed on the intrinsic silicon layer, and a source electrode and a drain electrode formed at contact parts of the pair of first impurity contained silicon layers; gate wiring for connecting the gate electrodes of the silicon thin film transistors to each other; and source wiring for connecting the source electrodes of the silicon thin film transistors to each other.

Silicon thin film transistor

A silicon thin film transistor array includes a plurality of silicon thin film transistors in an array-like form, each silicon thin film transistor including an insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating layer formed on the insulating substrate containing the gate electrode, a pair of first impurity contained silicon layers formed on the gate insulating layer in such a manner as to transversely cross a terminal part of the gate electrode, an intrinsic silicon layer formed on the pair of first impurity contained silicon layers and on the gate insulating layer between the pair of first impurity contained silicon layers in such a manner as to connect the pair of first impurity contained silicon layers, a protective insulation layer formed on the intrinsic silicon layer, and a source electrode and a drain electrode formed at contact parts of the pair of first impurity contained silicon layers; gate wiring for connecting the gate electrodes of the silicon thin film transistors to each other; and source writing for connecting the source electrodes of the silicon thin film transistors to each other.

A silicon thin film transistor array includes a plurality of silicon thin film transistors in an array-like form, each silicon thin film transistor including an insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating layer formed on the insulating substrate containing the gate electrode, a pair of first impurity contained silicon layers formed on the gate insulating layer in such a manner as to transversely cross a terminal part of the gate electrode, an intrinsic silicon layer formed on the pair of first impurity contained silicon layers and on the gate insulating layer between the pair of first impurity contained silicon layers in such a manner as to connect the pair of first impurity contained silicon layers, a protective insulating layer formed on the intrinsic silicon layer, and a source electrode and a drain electrode formed at contact parts of the pair of first impurity contained silicon layers; gate wiring for connecting the gate electrodes of the silicon thin film transistors to each other; and source wiring for connecting the source electrodes of the silicon thin film transistors to each other.

A method for producing a reverse staggered type silicon thin film transistor includes the steps of forming a gate insulating layer on a substrate having a gate electrode, the gate insulating layer having a transistor-forming portion; forming an intrinsic silicon film on the transistor-forming portion of the gate insulating layer; forming an n-type silicon layer on the intrinsic silicon layer; forming a source electrode on the n-type silicon layer; forming a drain electrode on the n-type silicon layer; forming a resist layer on the source electrode and drain electrode and having the same shape thereof; subsequently removing a portion of the n-type silicon layer by using the resist layer as a mask, such that there remains a predetermined thickness of the n-type silicon layer; and doping the predetermined thickness of the n-type silicon layer with p-type impurities by using the resist layer as a mask.

Method for producing reverse staggered type silicon thin film transistor

Silicon thin film transistor with an intrinsic silicon active layer

Silicon thin film transistor and method for producing the same

A method for manufacturing an amorphous silicon thin film transistor in which a gate insulating layer is provided over a gate on a substrate. An amorphous silicon layer is formed on the gate insulating layer, and a protective insulating layer is formed on the amorphous silicon layer. A pattern conforming to the gate is applied to the protective layer, and the amorphous layer is exposed in regions outside of the pattern. A doped silicon layer is then added, and source and drain electrodes formed to partly overlap the remaining protective insulating layer.

Method of manufacturing amorphous-silicon thin-film transistors

Method for producing a silicon thin film transistor

An amorphous silicon thin film transistor array substrate is formed on an insulating substrate with a gate insulating layer, as gate wiring itnerconnecting gate electrodes and source wiring interconnecting source electrodes. The gate insulating layer is provided in a lower layer of a terminal part of the source wiring. In the process for forming the array, the gate insulating layer is formed in a portion of the structure other than the terminal part of the gate, and the terminal part of the source wiring is formed on the gate insulating layer.

Amorphous silicon thin film transistor array substrate and method for

A reverse staggered type silicon thin film transistor includes a substrate having a gate electrode; a gate insulating layer on the substrate and the gate electrode, the gate insulating layer having a transistor-forming portion; a lower layer silicon film on the transistor-forming portion of the gate insulating layer and in contact therewith, the lower layer silicon film being formed at a first temperature and with a first thickness; an upper layer silicon film formed on the transistor-forming portion of the gate insulating layer at a second temperature which is lower than the first temperature and with a second thickness greater than the first thickness; an n-type silicon layer on the upper layer silicon film and in contact therewith; a source electrode on the n-type silicon layer; and a drain electrode on the n-type silicon layer.

Method of fabricating a reverse staggered type silicon thin film

A reverse staggered amorphous silicon thin film transistor array substrate includes an array of amorphous silicon thin film transistors, gate wiring interconnecting the gate electrodes of the amorphous silicon thin film transistors, and source wirings. The transistor array is provided on a thin film transistor array substrate. A protective insulation layer and an amorphous silicon layer having a greater width than the source wiring are provided under the source wiring.

Growing community of inventors

Tokyo, Japan

Sakae Tanaka