Hitachi, Ltd.

Sakae Miki

Kenji Kawakita

Kenji Iimura

Hiroshi Takahashi

Shunji Shimada

Yusuke Takeuchi

Michio Hara

Kenichi Kimura

Akira Ikuta

Kenjirou Yasunari

A system of adding an operand address included in an instruction word to the contents of a modification register to obtain an effective address, wherein address data which designates each of a plurality of data tables constituted with prescribed storage capacity, is stored in a plurality of modification registers. Prescribed address data of one of the plurality of modification registers is selected based on the instruction word. The effective address for addressing the operand is obtained by adding the prescribed address data of the one of the plurality of modification registers to address data included in the operand address. The address data included in the operand address designates addresses which correspond to addresses of the plurality of data tables.

Operand address modification system

A multichannel communication processing system having line control apparatus means for analyzing receiving frames and channel-controlling transmitting frames, DMA control apparatus for transferring the data not via a host processor but directly to a main memory, a memory for storing a variety of data and a communication protocol processing program, a CPU for controlling the communication processing system as a whole and line correspondence apparatus including line correspondence units provided between the lines and the line control apparatus whereby serial interfaces with channels of the plurality of lines are effected.

Multichannel communication processing system

Disclosed is a DMA controller incorporated in a data processor, comprising a plurality of channels and a control circuit for overseeing these channels. Each of these channels has registers for storing transfer parameters (address and byte count), registers for storing control parameters (status and command), data assembler circuit, and a channel control circuit that controls these registers and data assembler circuits. The channel control circuit in each channel simultaneously processes transfer parameters for an increased data transmission rate and a reduction of the internal processing unit work load.

Single chip communication data processor with direct memory access

Disclosed is a communication control microcomputer which includes components that implement serial communication control in compliance with a communication protocol, a FIFO memory for temporarily holding transaction data, a direct memory access control (DMAC) for implementing DMA transfer between the FIFO memory and the main memory, and a CPU for implementing general control over these components. A signal indicating end of frame (transaction data) is passed between components that control the serial communication and the DMAC through the FIFO memory.

Growing community of inventors

Tokyo, Japan

Sakae Miki