Mitsubishi Denki Kabushiki Kaisha

Other

International Business Machines Corporation

Mitsubishi Electric System Lsi Design Corporation

Sakae Itoh

Tatsuya Sakai

Teruaki Kanzaki

Yasuhiro Nakamura

Masayuki Murakami

Hiroshi Uchiike

Hiroshi Ueki

Tsutomu Numata

Tadayuki Akatsuki

A debug circuit ( ) and a microcomputer incorporating the debug circuit ( ). The debug circuit ( ) is capable of receiving a trace event from a functional block A as long as a CPU ( ) does not generate any trace event, and capable of receiving the trace event from the functional block A in synchronization with a standard clock signal CLK used in the CPU ( ) when the reception of the trace event from the functional block A is permitted.

Debug circuit and microcomputer incorporating debug circuit

A system LSI has a MPU and a HDC ( ) in which the HDC ( ) incorporates a CIU ( ). The CIU ( ) decodes addresses transferred from a CPU ( ), reads program codes stored in memories such as a ROM ( ) and a SRAM ( ) in the HDC ( ) when the addresses indicate memory fields in the memories, and outputs the obtained program codes to the CPU ( ).

LSI system capable of reading and writing at high speed

A computer program product, method and apparatus for utilizing common prefix codes in computing instructions so as to reduce the number instructions required to perform identical operations for varying operand sizes. In one form, the common prefix code is appended as the higher order portion of the instruction word to form a second series of instructions. These computing instructions may be utilized in conjunction with a flag register, which, in one application, designates which series of instructions to use; either the original instructions or the modified instructions containing the common prefix. In another application, the flag register designates which register or memory should be used to store the operands and the associated results. Through the use of common prefix codes and the flag register, operands of various sizes can be efficiently manipulated through a simplified scheme of instructions.

Instruction set and executing method of the same by microcomputer

A microcomputer contains an electrically erasable flash memory for storing a program under development and a debugging circuit 7 having a dedicated input/output terminal for connection to an external ICE 14, and the debugging circuit 7 has a function of communication with a CPU 1, a function of communication with the ICE 14, a function of tracing the operating condition of the CPU 1, a break function of generating a debug interrupt, a function of writing a program code from the ICE 14 into the flash memory 6 and a function of sending the contents of the flash memory 6 to the ICE 14.

Microcomputer

A delay clock signal is generated by delaying an input clock signal by a predetermined time interval with a delay circuit, and is subjected to frequency division with a frequency divider circuit to generate a reference clock signal. This delay clock signal and the input clock signal are provided to a flip-flop to generate a first electronic state signal when the input clock signal turns from 'High' to 'Low', and a second electronic state signal when the reference clock signal turns from 'High' to 'Low', and to electronically activate a control object during the time the second electronic state signal is inputted.

Delay circuit

A microcomputer in which a higher address must be corrected according to a carry or borrow signal generated during address computation for memory reference based on each addressing mode. The microcomputer is provided with a databank register for holding the higher address and a temporary register for storing a value obtained by incrementing or decrementing by one digit the contents of the data bank register so that the higher order address may be corrected with neither increase in the number of instruction executing cycles nor loss of the memory area continuity.

Memory bank address calculation with reduced instruction execution cycles

A method and apparatus for fast branching of microcode sequences in a microcomputer. A branch controller provides addresses to a microcode memory and receives addresses and a branch control signal back from the memory for the next microcode to be executed. Prior to determining whether a branch instruction is present at the indicated location in the sequence, the branch controller provides a provisional address to the memory for the next sequential microcode in the sequence assuming that no branching is to occur. Then a determination is made whether a branch instruction is present. If so, the provisional address is changed by inverting one or more address bits to reflect the branching address and the changed address is applied within the same cycle to the memory.

Microcode control system in a microcomputer capable of branching to

A microcomputer system including an EPROM (electrically programmable read-only memory) which can be programmed either externally or by the control processing unit of the system. The control means, normally responsive to externally applied control signals, is disabled by a register of the system which can be set by the control processing unit and by an address decoder connected to the address bus.

Growing community of inventors

Hyogo, Japan

Sakae Itoh