Intel Corporation

Sajjad A Zaidi

Michael Mantor

Andrew M Volk

Aditya Sreenivas

Satyaki Koneru

Kam Leung

Brian D Rauchfuss

John A Carey

Eric B Selvin

R Scott Hartog

Embodiments of the present invention provide a method and apparatus for determining the zones that a polygon overlaps to minimize the bins that are updated during binning and reduce the number of polygons to be set up in the render phase. The polygons supported include, but are not limited to, points, lines, triangles and rectangles. Each zone has associated with it a batch buffer to which data is written back for the polygons that overlap that zone. This data includes the setting up of state and the indices for those polygons. Since the zones that a polygon overlaps is precisely determined, the data written back is minimized and the polygons to be set up during the render phase is optimally reduced.

Method and apparatus for determining bins to be updated for polygons, including lines

A pipeline apparatus for processing 3D graphics data will be described. The pipeline apparatus includes a first request memory to fetch information corresponding to a texture operand. A second request memory fetches information responding to a color operand and Z operand. A control circuit coordinates data flow from the first request memory and the second request memory into a memory channel by preventing the number of requests from the first request memory from exceeding by a predetermined number, the number of requests from the second request memory. By properly coordinating the data flow, deadlock of a data fetching pipeline is avoided.

Data skew management of multiple 3-D graphic operand requests

A voltage supply isolation buffer which prevents a voltage applied to an input or output of an IC device from reaching the power supply plane of the device. An inverter circuit is modified such that Vdd is coupled to the source of the p-channel pull-up transistor through a pn diode with the p terminal coupled to Vdd and the n terminal coupled to the source of the p-channel transistor. Under normal operation, Vdd forward biases the diode allowing a high voltage to be applied to the output of the inverter circuit when the p-channel transistor turns on. If, however, a voltage is applied to the output of the inverter circuit by an external voltage supply which is higher than Vdd, the diode will be reverse biased, preventing the voltage at the output node from raising the Vdd level.

Voltage supply isolation buffer

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El Dorado Hills, CA, United States of America

Sajjad A Zaidi