Qualcomm Incorporated

Sajin Mohamad

Harikrishna Chintarlapalli Reddy

Suresh Naidu Lekkala

Chulkyu Lee

Rakesh Kumar Sinha

Pradeep Kumar Sana

Abhinav Murali

Jonathan Holland

Jibu Varghese K

Neha Agrawal

An integrated circuit (IC), including: a current mirror, including: a first field effect transistor (FET) including a first drain, a first gate, and a first source, wherein the first source is coupled to a first voltage rail; and a second FET including a second drain, a second gate, and a second source, wherein the second gate is coupled to the first gate of the first FET, and the second source is coupled to the first voltage rail; and a selective coupling circuit configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a voltage at the first drain of the first FET.

Bias current receiver with selective coupling circuit

A bandwidth enhanced amplifier for high frequency CML To CMOS conversion is disclosed. In some implementations, an improved CML to CMOS converter includes a differential amplifier having a first and a second input transistors, and a first and a second load transistors. The first input transistor is coupled in series with the first load transistor, and the second input transistor is coupled in series with the second load transistor. The improved CML to CMOS converter further includes a first capacitor and a second capacitor. The first capacitor is coupled directly between a gate of the first input transistor and a gate of the first load transistor.

Bandwidth enhanced amplifier for high frequency CML to CMOS conversion

Certain aspects of the present disclosure generally relate to a sampling circuit, such as a sampling circuit for a low-voltage differential signaling (LVDS) serializer/deserializer (SerDes) system. One example sampling circuit generally includes a latching circuit and a plurality of pass-gate transistors. The latching circuit includes differential inputs, differential outputs, a clocked input circuit coupled to the differential inputs, a first cross-coupled circuit coupled to the clocked input circuit, and a second cross-coupled circuit coupled to the first cross-coupled circuit, wherein the first and second cross-coupled circuits are coupled to the differential outputs of the latching circuit. Each pass-gate transistor is coupled between one of the differential inputs of the latching circuit and a corresponding differential input of the sampling circuit.

Zero hold time sampler for low voltage operation

An IC includes an array of cells and a first set of endcap cells. The array of cells includes a first set of Mlayer power interconnects coupled to a first voltage, a first set of Mlayer interconnects, a second set of Mlayer power interconnects coupled to a second voltage source, and a second set of Mlayer interconnects. The first set of endcap cells includes first and second sets of Mlayer interconnects. The first set of Mlayer interconnects is coupled to the first set of Mlayer power interconnects and to the second set of Mlayer interconnects to provide a first set of decoupling capacitors. The second set of Mlayer interconnects is coupled to the second set of Mlayer power interconnects and to the first set of Mlayer interconnects to provide a second set of decoupling capacitors.

Cell architecture with intrinsic decoupling capacitor

Systems and methods for dividing input clock signals by programmable divide ratios can produce output clock signals with the delay from the input clock signal to the output clock signal independent of the value of the divide ratio and with the duty cycle of the output clock signal being 50% independent of the value of the divide ratio. An example programmable clock divider includes a modulo N counter that produces a count signal that counts modulo the divide ratio and a half-rate clock signal generator that produces a common half-rate clock signal, an even half-rate clock signal, and an odd half-rate clock signal that toggle at one-half the rate of the output clock signal. The common half-rate clock signal, the even half-rate clock signal, and the odd half-rate clock signal are combined to produce the output clock signal.

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Bengaluru, India

Sajin Mohamad