Chartered Semiconductor Manufacturing Ltd (corporation)

Sajan Marokkey Raphael

Juan Boon Tan

Sanford Chu

Chit Hwei Ng

Lup San Leong

Chaw Sing Ho

Raymond Joy

Shao Kai

Fang Hong Gn

Tak Yan Tse

An improved process for fabricating simultaneously high capacitance, less than 0.13 micron metal-insulator-metal capacitors, metal resistors and metal interconnects, has been developed using single or dual damascene processing. The key advantage is the use of only one additional mask reticle to form both MIM capacitor and resistor, simultaneously. Several current obstacles that exist in BEOL, back end of line, are overcome, namely: (a) the use of two or more photo-masks to make <0.13 um MIM capacitors, (b) undulated copper surfaces, when dielectrics are deposited directly upon it, (c) particles generation concerns during etching, when attempting an etch stop on the bottom MIM plate layers, and finally, (d) dishing during CMP occurs when large copper MIM plates are required, with subsequent capacitance matching problems. The integrated method overcomes the above obstacles and simultaneously forms MIM capacitors, metal resistors and metal interconnects using damascene processing. In addition, the method of forming the MIM capacitors, described herein, can also be used to form anti-fuse devices, in field-programmable gate arrays, FPGA.

MIM and metal resistor formation at CU beol using only one extra mask

A method for checking the position of alignment marks after a chemical mechanical polishing (CMP) process and automatically compensating for alignment of a wafer stepper based on the position checking is described. A wafer is provided having an alignment mark thereon for the purpose of aligning a reticle in the wafer stepper. The wafer is polished by CMP. Thereafter, alignment mark positioning is checked for deviation from a normal vectorial position of the alignment mark whereby information about the deviation is fed back to the wafer stepper and wherein the wafer stepper automatically compensates for correctable alignment error based on the deviation information.

Accurate wafer patterning method for mass production

Growing community of inventors

Singapore, Singapore

Sajan Marokkey Raphael