Nxp B.v.

St-ericsson Sa

Nytell Software LLC

Sainath Karlapalem

Nagaraju Bussa

Bijo Thomas

Andrei Sergeevich Terechko

Narendranath Udupa

Various exemplary embodiments relate to a radar device for detecting objects that intersect an area, the device including a mount attachment; a radar sensor; an output interface; a memory storing one or more environment parameters; a processor in communication with the radar sensor, the output interface, and the memory, the processor being configured to: receive, from the radar sensor, signal information; retrieve, from the memory, environment parameters; calculate, based on the signal information, the distance relative to the sensor of one or more objects; calculate an area based on at least one of the environment parameters; and determine that at least one of the one or more objects intersect the area.

Personal radar assistance

A circuit contains a shared memory (), that is used by a plurality of processing elements () that contain cache circuits () for caching data from the shared memory (). The processing elements perform a plurality of cooperating tasks, each task involving caching data from the shared memory () and sending cache message traffic. Consistency between cached data for different tasks is maintained by transmission of cache coherence requests via a communication network. Information from cache coherence requests generated for all of said tasks is buffered. One of the processing elements provides an indication signal indicating a current task stage of at least one of the processing elements. Additional cache message traffic is generated adapted dependent on the indication signal and the buffered information from the cache coherence requests. Thus conditions of cache traffic stress may be created to verify operability of the circuit, or cache message traffic may be delayed to avoid stress.

Circuit and method with cache coherence stress control

A data processing system is provided with at least one processing unit () for an interleaved processing of multiple tasks (T-T), and a cache () associated to the at least one processing unit () for caching data for the multiple tasks (T-T) to be processed by the at least one processing unit (). The cache () is divided into a plurality of cache lines (). Each of the cache lines () is associated to one of the multiple tasks (T-T). Furthermore, a task scheduler () is provided for scheduling the multiple tasks (T-T) to be processed in an interleaved manner by the at least one processing unit (). A cache controller () is provided for selecting those cache lines () in the cache (), which are to be evicted from the cache (). This selection is performed based on the task scheduling of the task scheduler ().

Data processing system and method for cache replacement using task scheduler

A data processing system is provided comprising at least one processing unit (PU) for data processing and a debugger means (DM) for debugging the processing of the at least one processing unit (PU) based on a plurality of breakpoints. The debugger means (DM) comprises a first register (BAR) for storing a base address for one of the plurality of breakpoints, wherein the debugging means (DM) initiates the debugging of the processing of the at least one processing units (PU) based on the base address stored in the first breakpoint register, i.e. the base address register. A second breakpoint register (OR) is provided for storing an offset for obtaining subsequent breakpoints. A logic arithmetic unit (LAU) is provided for repetitively calculating a breakpoint condition based on the base address stored in the first breakpoint register and the offset stored in the second breakpoint register and for updating the base address stored in the first breakpoint register.

Means and method for debugging

A data processing system is provided comprising at least one processing unit for processing data; a memory means for storing data; and a cache memory means for caching data stored in the memory means. Said cache memory means is associated to at least one processing unit. An interconnect means is provided for connecting the memory means and the cache memory means. The cache memory means is adapted for performing a cache replacement based on reduced logic level changes of the interconnect means as introduced by a data transfer between the memory means and the cache memory means.

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Bengaluru, India

Sainath Karlapalem