Agere Systems Inc.

Agere Systems Guardian Corp.

Lucent Technologies Inc.

Lsi Corporation

At+t Corp.

Avago Technologies General IP (singapore) Pte. Ltd.

Other

Sailesh Mansinh Merchant

Pradip Kumar Roy

Sailesh Chittipeddi

Sudhanshu Misra

Mark Adam Bachman

Seung Hyuk Kang

Daniel Patrick Chesire

Isik C Kizilyalli

Edward Belden Harris

Taeho Kook

Siddhartha Bhowmik

John William Osenbach

Nace Layadi

Kurt George Steiner

Arun Kumar Nanda

William Graham Easter

Susan Clay Vitkavage

Hem M Vaidya

Joseph William Buckfeller

Yifeng Winston Yan

Subramanian Karthikeyan

Minseok Oh

Yi Ma

Frank Miceli

Seungmoo Choi

Kouros Azimi

Joseph Rudolph Radosevich

Larry Bruce Fritzinger

Binh Nguyenphu

Vance D Archer, Iii

Simon John Molloy

Annette Margaret Crevasse

Vivian Wanda Ryan

Sundar Srinivasan Chetlur

John A Maze, Iii

Sidhartha Sen

Donald Stephen Bitting

Vance Dolvan Archer

Warren K Gladden

Mindaugas Fernand Dautartas

John Albert Maze, Iii

Yuanning Chen

Glenn B Alers

Daniel Joseph Vitkavage

Casimir R Nijander

Michael F Brady

Stephen Ward Downey

James F Dormer

James Theodore Clemens

Philip William Seitzer

Joze E Antol

Cheryl Anne Bollinger

Edward Alan Dein

Deepak A Ramappa

Cletus Walter Wilkins, Jr

Michael C Ayukawa

Frank Minardi

Rafe Carl Mengel

Daniele Gilkes

Thomas B Gans

Mohammad Shafiul Mobin

Roger A Fratti

Kuo-Hua Lee

Yiu-Huen Wong

Charles Walter Pearce

Michael Louis Steigerwald

Kenneth Wade Paist

Leonard Jay Olmer

Richard William Gregor

Vivek Saxena

William M Moller

Mahjoub Ali Abdelgadir

Martin G Meder

Seong Jin Koh

Darrell L Simpson

Isaiah O Oladeji

Adrienne Gould-Choquette

Jean Ling Lee

Lisa E Mullin

G Craig Clabough

Isik C Kizilayalli

Robert Wayne Bradshaw

Ronald Joseph Schutz

Roland P Krebs

Pei H Yih

Steven Mark Anderson

Jaseph R Radosevich

Pradip Kimar Roy

A method of manufacturing an IC, comprising providing a substrate having a first side and a second opposite side, forming a STI opening in the first side of the substrate and forming a partial TSV opening in the first side of the substrate and extending the partial TSV opening. The extended partial TSV opening is deeper into the substrate than the STI opening. The method also comprises filling the STI opening with a first solid material and filling the extended partial TSV opening with a second solid material. Neither the STI opening, the partial TSV opening, nor the extended partial TSV opening penetrate an outer surface of the second side of the substrate. At least either: the STI opening and the partial TSV opening are formed simultaneously, or, the STI opening and the extended partial TSV opening are filled simultaneously.

Integration of shallow trench isolation and through-substrate vias into integrated circuit designs

A heat spreader that is configured to be attached to an integrated circuit substrate. The heat spreader includes a thermally conductive core and a heat spreader via that passes through the thermally conductive core. A connection point of the thermally conductive core is configured to form a solder connection to an integrated circuit substrate plug.

Stacked interconnect heat sink

A method of manufacturing a through-substrate-via structure. The method comprises providing a substrate having a front-side and an opposite back-side. A through-substrate via opening is formed in the front-side of the substrate. The through-substrate-via opening does not penetrate an outer surface of the back-side of the substrate. The through-substrate-via opening is filled with a solid fill material. Portions of the substrate from the outer surface of the back-side of the substrate are removed to thereby expose the fill material. At least portions of the exposed fill material are removed to form a back-side through-substrate via opening that traverses an entire thickness of the substrate. The back-side through-substrate via opening is filled with an electrically conductive material.

Method of fabrication of through-substrate vias

Systems and methods for authenticating electronic devices may perform one or more operations including, but not limited to: receiving at least one code associated with an authorization to perform one or more manufacturing life-cycle operations for at least one electronic device; and blowing one or more fuses of the at least one electronic device according to the at least one code associated with an authorization to perform one or more manufacturing life-cycle operations for the at least one electronic device.

Preventing electronic device counterfeits

The invention provides, in one aspect, a semiconductor device that comprises an interconnect layer located over a semiconductor substrate. A passivation layer is located over the interconnect layer and having a solder bump support opening formed therein. Support pillars that comprise a conductive material are located within the solder bump support opening.

Solder bump structure for flip chip semiconductor devices and method of manufacturing therefore

An electronic device includes an integrated circuit and a heat spreader. The integrated circuit includes a substrate with an active via located therein. The heat spreader includes a thermally conductive core. The active via is connected to a corresponding heat spreader via that passes through the thermally conductive core.

The present invention provides a solder bump structure. In one aspect, the solder bump structure is utilized in a semiconductor device, such as an integrated circuit. The semiconductor device comprises active devices located over a semiconductor substrate, interconnect layers comprising copper formed over the active devices, and an outermost metallization layer positioned over the interconnect layers. The outermost metallization layer comprises aluminum and includes at least one bond pad and at least one interconnect runner each electrically connected to an interconnect layer. An under bump metallization layer (UBM) is located over the bond pad, and a solder bump is located over the UBM.

Routing under bond pad for the replacement of an interconnect layer

The invention, in one aspect, provides a semiconductor device (), including transistors (), dielectric layers () located over the transistors (), interconnects () formed within the dielectric layers (), and a test structure () located adjacent a hot-spot () of the semiconductor device () and configured to monitor a real-time operational parameter of at least one of the transistors () or interconnects ().

Thermal monitoring and management of integrated circuits

Solder bump structure for flip chip semiconductor devices and method of manufacture therefore

In described embodiments, elements of a wireless home network employ learned power security for the network. An access point, router, or other wireless base station emits and receives signals having corresponding signal strengths. Wireless devices coupled to the base station through a radio link are moved through the home network at boundary points of the home and the signal strength is measured at each device and communicated to the base station. Based on the signal strength information from the emitted signals measured at the boundary points and/or from measured signal strength information of signals received from the boundary points, the base station determines a network secure area. The base station declines permission of devices attempting to use or join the home network that exhibit signal strength characteristics less than boundary values for the network secure area.

Power learning security in wireless routers

A semiconductor test device includes a test circuit having contacts for applying an electrical signal and measuring electrical parameters of the test circuit. The semiconductor test device also includes an integrally formed heating circuit comprising at least one circuit meander positioned adjacent the test circuit for raising a temperature within a portion of the test circuit.

Semiconductor test device with heating circuit

A solder bump structure and an under bump metallurgical structure. An upper surface of a semiconductor substrate comprises a first conductive pad () disposed thereon. A passivation layer () overlies the upper surface. A second conductive pad () is disposed in an opening () in the passivation layer and in contact with the first conductive pad. The under bump metallurgical structure () encapsulates the second conductive pad, covering an upper surface and sidewalls surfaces of the second conductive pad, protecting both the first and the second conductive pads from environmental and processing effects. According to the present invention, the conventional second passivation layer is not required. Methods for forming the various structures are also presented.

Structure and method for fabricating flip chip devices

An integrated circuit structure includes a metallization level having a dual damascene trench structure formed in a layer of dielectric material. The dielectric material has an upper surface with a first degree of planarity. The metallization level includes a conductive layer formed in the trench structure with an upper surface characterized by the same level of planarity as the dielectric material upper surface. In certain embodiments, the upper surface of the conductive layer is substantially coplanar with the dielectric material upper surface.

Formation of an integrated circuit structure with reduced dishing in metallization levels

An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.

Inductor formed in an integrated circuit

Growing community of inventors

Orlando, FL, United States of America

Sailesh Mansinh Merchant