Intel Corporation

Sailesh Kottapalli

John H Crawford

Gilbert A Neiger

Richard A Uhlig

Henk G Neefs

David M Durham

Andrew V Anderson

Ronak Singhal

Vedaraman Geetha

Kushagra V Vaid

Rahul Pal

Xiangbin Wu

Dheemanth Nagaraj

Manoj K Arora

Udo Walterscheidt

Yen-Cheng Liu

Allen Jay Baum

Jeffrey D Chamberlain

Ken Shoemaker

James Steven Burns

Thomas Y Yeh

Andrew Y Sun

Kin-Kee Sit

Kinkee Sit

Mohan J Kumar

Glenn J Hinton

Rajesh M Sankaran

Robert G Blankenship

Raj K Ramanujan

Sanjay Kumar

Mahesh S Natu

Sujat Jamil

Joseph Nuzman

Herbert H Hum

Kai Cheng

Tse-Yu Yeh

Robert S Chappell

Andrew Thomas Forsyth

Brian S Morris

Kenneth D Shoemaker

Jonathan Cannon Hall

Michael Paul Corwin

James R Vash

Sham M Datta

Adrian C Moga

Judge K Arora

Scott P Bobholz

Bongjin Jung

Subramanya R Dulloor

Ganesh Kumar

Jeff Wiedemeier

Richard W Goe

Nadeem H Firasta

Youngsoo Choi

Neil J Achtman

Embodiments of an invention for monitoring the operation of a processor are disclosed. In one embodiment, a system includes a processor and a hardware agent external to the processor. The processor includes virtualization logic to provide for the processor to operate in a root mode and in a non-root mode. The hardware agent is to verify operation of the processor in the non-root mode based on tracing information to be collected by a software agent to be executed by the processor in the root mode.

Monitoring the operation of a processor

Methods and apparatus are disclosed for accessing multiple data cache lines for scatter/gather operations. Embodiment of apparatus may comprise address generation logic to generate an address from an index of a set of indices for each of a set of corresponding mask elements having a first value. Line or bank match ordering logic matches addresses in the same cache line or different banks, and orders an access sequence to permit a group of addresses in multiple cache lines and different banks. Address selection logic directs the group of addresses to corresponding different banks in a cache to access data elements in multiple cache lines corresponding to the group of addresses in a single access cycle. A disassembly/reassembly buffer orders the data elements according to their respective bank/register positions, and a gather/scatter finite state machine changes the values of corresponding mask elements from the first value to a second value.

Processor and method for tracking progress of gathering/scattering data element pairs in different cache memory banks

Methods and apparatus relating to improving the value of F-state by increasing a local caching agent's data forwarding are described. In one embodiment, the opportunity for forwarding from a local caching agent is improved by allowing the local caching agent to keep an F-state copy of the line while sending an S-state copy to the requestor (e.g., in response to a non-ownership read operation). Other embodiments are also disclosed.

Value of forward state by increasing local caching agent forwarding

An apparatus and method for reducing or eliminating writeback operations. For example, one embodiment of a method comprises: detecting a first operation associated with a cache line at a first requestor cache; detecting that the cache line exists in a first cache in a modified (M) state; forwarding the cache line from the first cache to the first requestor cache and storing the cache line in the first requestor cache in a second modified (M') state; detecting a second operation associated with the cache line at a second requestor; responsively forwarding the cache line from the first requestor cache to the second requestor cache and storing the cache line in the second requestor cache in an owned (O) state if the cache line has not been modified in the first requestor cache; and setting the cache line to a shared (S) state in the first requestor cache.

Cache coherency apparatus and method minimizing memory writeback operations

An apparatus and method are described for store durability and ordering in a persistent memory architecture. For example, one embodiment of a method comprises: performing at least one store operation to one or more addresses identifying at least one persistent memory device, the store operations causing one or more memory controllers to store data in the at least one persistent memory device; sending a request message to the one or more memory controllers instructing the memory controllers to confirm that the store operations are successfully committed to the at least one persistent memory device; ensuring at the one or more memory controllers that at least all pending store operations received at the time of the request message will be committed to the persistent memory device; and sending a response message from the one or more memory controllers indicating that the store operations are successfully committed to the persistent memory device.

Method and apparatus for store durability and ordering in a persistent memory architecture

In one embodiment, the present invention includes a method of assigning a location within a shared variable for each of multiple threads and writing a value to a corresponding location to indicate that the corresponding thread has reached a barrier. In such manner, when all the threads have reached the barrier, synchronization is established. In some embodiments, the shared variable may be stored in a cache accessible by the multiple threads. Other embodiments are described and claimed.

Synchronizing multiple threads efficiently

In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information is not present in a remote caching agent, and if so, transmitting the information from the memory location to the first caching agent before snoop processing with respect to the read request is completed. Other embodiments are described and claimed.

Extending a cache coherency snoop broadcast protocol with directory information

Systems and techniques for virtual device sharing. A failure of one of a plurality of memory devices corresponding to a first rank in a memory system is detected. The memory system has a plurality of ranks, each rank having a plurality of memory devices used to store a cache line. A portion of the cache line corresponding to the failed memory device is stored in a memory device in a second rank in the memory system and the remaining portion of the cache line in the first rank of the memory system.

Virtual device sparing

Methods and apparatus relating to dynamically routing data responses directly to a requesting processor core are described. In one embodiment, data returned in response to a data request is to be directly transmitted to a requesting agent based on information stored in a route back table. Other embodiments are also disclosed.

Dynamically routing data responses directly to requesting processor core

Growing community of inventors

San Jose, CA, United States of America

Sailesh Kottapalli