Lucent Technologies Inc.

Agere Systems Inc.

Agere Systems Guardian Corp.

At&t Bell Laboratories

At+t Corp.

Avago Technologies General IP Pte, Ltd.

Sailesh Chittipeddi

Sailesh Mansinh Merchant

Yehuda Smooha

William Thomas Cochran

Michael James Kelly

Pradip Kumar Roy

Charles Walter Pearce

Taeho Kook

Vivian Wanda Ryan

Arun Kumar Nanda

Avinoam Kornblit

Joseph William Buckfeller

Ankineedu Velaga

Seung Hyuk Kang

Mark Adam Bachman

Siddhartha Bhowmik

William T Cochran

Donald Stephen Bitting

Keelathur N Vasudevan

Stephen Knight

Kurt George Steiner

Seungmoo Choi

Steven Alan Lytle

Min-Liang Chen

Chong-Cheng Fu

Kang W Lee

Carlos M Chacon

Michael A Washko

Tungsheng Yang

Richard A Powell

Wan Yee Cheung

Michael J Toth

Robert T Smith

Mamata Patnaik

Richard J Jenkins

Thomas N Hofacker

Daryl E Diehl

Michael J Kelly

The invention provides, in one aspect, a semiconductor device that comprises an interconnect layer located over a semiconductor substrate. A passivation layer is located over the interconnect layer and having a solder bump support opening formed therein. Support pillars that comprise a conductive material are located within the solder bump support opening.

Solder bump structure for flip chip semiconductor devices and method of manufacturing therefore

A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. A variety of silicided and non-silicided) structures may be formed.

Transistor fabrication method

Solder bump structure for flip chip semiconductor devices and method of manufacture therefore

An integrated circuit structure includes a metallization level having a dual damascene trench structure formed in a layer of dielectric material. The dielectric material has an upper surface with a first degree of planarity. The metallization level includes a conductive layer formed in the trench structure with an upper surface characterized by the same level of planarity as the dielectric material upper surface. In certain embodiments, the upper surface of the conductive layer is substantially coplanar with the dielectric material upper surface.

Formation of an integrated circuit structure with reduced dishing in metallization levels

An integrated circuit device having a capacitor structure. In one form of the invention, an integrated circuit device includes a capacitor structure formed along a surface of a semiconductor layer. The capacitor structure includes a region formed in the semiconductor surface, a layer of dielectric material formed along a trench wall of the trench region and a first layer of doped polysilicon formed over the layer of dielectric material in the trench region. The capacitor structure further includes a second layer of doped polysilicon formed over the first layer of polysilicon.

Integrated circuit with a trench capacitor structure and method of manufacture

A bond pad is located over active circuitry formed within an integrated circuit device. A barrier film forms the bottom surface of the upper portion of a bond pad opening which also includes vias extending through the bottom surface to form a dual damascene structure. The bond pad is resistant to stress effects such as cracking, which can be produced when bonding an external wire to the bond pad, and therefore prevents leakage currents between the bond pads and the underlying circuitry.

Dual damascene bond pad structure for lowering stress and allowing circuitry under pads

The present invention uses wire bonding technology to bond interconnect materials that oxidize easily by using a wire with stable oxidation qualities. A passivation layer is formed on the semiconductor substrate to encapsulate the bonding pad made from the interconnect material such that the wire bonds with the passivation layer itself, not with the interconnect material. The passivation layer is selected to be a material that is metallurgically stable when bonded to the interconnect material. Since the wire is stable compared with the interconnect material, i.e., it does not readily corrode, a reliable mechanical and electrical connection is provided between the semiconductor device (interconnect material) and the wire, with the passivation layer disposed therebetween.

Wire bonding method for copper interconnects in semiconductor devices

An architecture and process for forming CMOS vertical replacement gate metal oxide semiconductor field-effect transistors is disclosed. The integrated circuit structure includes a semiconductor area with a major surface formed along a plane and first and second source/drain dopes regions formed in the surface. An insulating trench is formed between the first and second source/drain regions. A third doped region forming a channel of a different conductivity type than the first source/drain region is positioned over the first source/drain region. A fourth doped region is formed over the second source/drain region, having an opposite conductivity type with respect to the second source/drain region, and forming a channel region. Fifth and sixth source/drain regions are formed respectively over the third and fourth doped regions. In an associated method of manufacturing the semiconductor device, first and second source/drain regions are formed in the semiconductor layer, followed by the formation of third and fourth doped regions forming the channel. Fifth and sixth doped regions are then formed over the channels to complete the structure. An insulating region is formed between the first and the second source/drain regions to isolate these regions of opposite conductivity type.

CMOS vertical replacement gate (VRG) transistors

The present invention is directed to a process for forming a dual damascene structure and a capacitor. The process includes forming a stack including insulating layers and a stop layer. The stack is patterned so that the openings used to form the sidewall capacitors may be formed when the vias or grooves of the dual damascene structure is formed. In this way, the process for manufacturing the sidewall capacitors may be integrated with the dual damascene process without adding additional mask or etching steps.

Process for manufacturing an integrated circuit including a dual-damascene structure and a capacitor

The present invention provides a method of forming a vertical replacement gate (VRG) device on a semiconductor substrate. The method includes depositing an epitaxial layer over a first source/drain region, implanting a layer within the epitaxial layer wherein the thickness of the layer substantially defines a channel length of the device and replacing the layer with a gate layer.

Method of forming a semiconductor device

The present invention provides a die located on a semiconductor wafer. In one embodiment, the die includes a circuit region located within a circuit perimeter of the die. In addition, the die includes a bond pad region located between the circuit perimeter and an outer perimeter of the die. Also the die includes an alignment mark located within the bond pad region.

Integrated circuit die having alignment marks in the bond pad region and method of manufacturing same

A Method and computer implemented system may be used to value knowledge-based property such as documents, databases, spreadsheets or research and development related information or studies. Intangible property may be valued by analyzing stored data representing accesses by users to a medium containing a copy of the knowledge-based property, estimating a pattern of the accesses by users to the medium containing the copy of the knowledge-based property using a statistical model, and assigning a value to the knowledge-based property based on the pattern. The data may comprise the total number of times the copy of the knowledge-based property has been accessed and a time-date stamp for each access event. The assigned values for a plurality of knowledge-based properties may then be used as bases for making decisions such as apportioning budget resources among tasks or projects related to the knowledge-based properties or apportioning availability of limited computer resources for storing shared documents.

Method and system for evaluating technology transfer value

An integrated circuit that includes I/O circuitry that may or may not be protected from ESD damage. The protection from ESD damage may be selectively deactivated or activated or may not be present at all in one or more of the I/O circuits. In use, the integrated circuit may be coupled to another integrated circuit to form a multi-chip module where the ESD protection for the I/O circuitry between the modules is deactivated or not present. This is advantageous because the likelihood of ESD damage to this I/O circuitry is reduced once the multi-chip module is formed. It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.

Integrated circuit including ESD circuits for a multi-chip module and a method therefor

A trench capacitor formed on an SOI substrate extends through an upper silicon layer and an insulating layer and into a semiconductor base substrate. The outer electrode of the trench capacitor includes portions of the semiconductor base substrate which bound the trench in which the trench capacitor is formed. The outer electrode is coupled to a contact structure formed in close proximity to the trench capacitor, and which extends through the insulating layer. The method for simultaneously producing the trench capacitor and contact structure includes forming two trench openings, forming a dielectric liner on one of the trench openings, then filling each of the trench openings with a semiconductor material.

Trench capacitors in SOI substrates

A semiconductor device comprising a silicon-on-insulator (SOI) substrate including a base substrate, an insulator layer, and a silicon layer, and a trench capacitor including at least one trench formed in the silicon-on-insulator substrate and extending through the base substrate, the insulator layer and the silicon layer, wherein the at least one trench includes at least one layer of silicon dioxide formed therein. In a preferred embodiment, semiconductor material disposed in the at least one trench forms a first electrode of a semiconductor capacitor, and semiconductor material of the SOI substrate which lies adjacent to the at least one trench forms a second electrode of the capacitor.

Silicon-on-insulator (SOI) semiconductor structure with additional trench including a conductive layer

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Allentown, PA, United States of America

Sailesh Chittipeddi