Technische Universiteit Delft

Cognitive Ic B.v.

Said Hamdioui

Mottaqiallah Taouil

Koenraad Laurent Maria Bertels

Zaid Al-Ars

Georgi Nedeltchev Gaydadjiev

Adrianus Van De Goor

Fethulah Smailbegovic

Cezar Rodolfo Wedig Reinbrecht

Method for testing an integrated circuit device, by defect modelling of the integrated circuit device, fault modelling of the integrated circuit device based on the information obtained from the defect modelling, test development based on information obtained from the fault modelling, and executing the test on the integrated circuit device. Defect modelling of the integrated circuit device including executing a physical defect analysis of the integrated circuit device to provide a set of effective technology parameters modified from a set of defect-free technology parameters associated with the integrated circuit device, and executing an electrical modelling of the integrated circuit device using the set of effective technology parameters to provide a defect-parametrized electrical model based on a defect-free electrical model of the integrated circuit device. The present methods allow parts-per-billion testing capabilities.

Device aware test for memory units

Integrated circuit device having a processor module () in communication with a cache memory module (), and one or more memory control modules () each arranged to interface with an associated storage memory unit (). An authentication module () is provided in communication with the memory control modules () and the cache memory modules (). The authentication module () is arranged to generate and store a hardware based secure key, read a predetermined set of data from the associated storage memory units (), and an associated stored hash value, calculate a hash value of the predetermined set of data using the hardware based secure key; and store the predetermined set of data in the cache memory module () only if the calculated hash value corresponds to the associated stored hash value.

Integrated circuit device with an authentication module

A computing device includes a computation circuit and a data storage circuit. The computation circuit is coupled to the data storage circuit and is arranged for reading and writing data from/to the data storage circuit. The computing device includes a memory array of non-volatile memory elements and controlling circuitry connected to the memory array for reading and writing data from/to selected memory elements in the array. The computation circuit and the data storage circuit are located in the memory array, and the non-volatile memory elements of the memory array are memristor-type elements.

Computing device for 'big data' applications using memristors

Method for testing a memory under test () including a plurality of memory cells and a Memory Built-In Self-Test Engine () connectable to a memory under test. The MBIST engine () is arranged to generate appropriate addressing and read and/or write operations to the memory under test (). The MBIST engine () is connected to a March Element Stress register (MESR) (), a generic march element register (GMER) (), and a Command Memory (). The GMER () specifies one of a set of Generic March Elements (GME), and the MESR () specifies the stress conditions to be applied. Only a few GMEs are required in order to specify most industrial algorithms. The architecture is orthogonal and modular, and all speed related information is contained in the GME. In addition, only little memory is required for the specification of the test, providing a low implementation cost, yet with a high flexibility.

Growing community of inventors

Delft, Netherlands

Said Hamdioui