Amazon Technologies, Inc.

Other

Annapuma Labs Ltd.

Said Bshara

Nafea Bshara

Erez Izenberg

Georgy Machulsky

Netanel Israel Belgazal

Adi Habusha

Evgeny Schmeilin

Jonathan Cohen

Gil Stoler

Avigdor Segal

Noam Katz

Leah Shalev

Alan Michael Judge

Barak Wasserstrom

Yaniv Shapira

Brian William Barrett

Alexander Matushevsky

Julien Ridoux

Joshua Benjamin Levinson

Jonathan Chocron

Tal Zilcer

Akram Baransi

Amiram Lifshitz

Omri Itach

Anthony Nicholas Liguori

Benjamin Charles Serebrin

Guy Nakibly

Filippo Sironi

Saar Gross

Clint Joseph Sbisa

Ronen Shitrit

Robert Klein

Anna Rom-Saksonov

Shadi Ammouri

Nitzan Zisman

Noam Attias

Rotem Shaanan

Dror Fleischmann

An input/output (I/O) device is coupled to a processor via a first peripheral bus and a second peripheral bus. The I/O device is configured to expose a first physical function (PF) and a second PF to a virtual machine (VM) executing on the processor. A first virtual function (VF) associated with the first PF is assigned to the first peripheral bus, and a second VF associated with the second PF is assigned to the second peripheral bus. The first VF and the second VF are exposed as a single VF to the VM. The VM can perform transactions with the I/O device via the single VF using the first peripheral bus and the second peripheral bus.

Bonding multiple peripheral ports to a single virtual machine

A wake-up management circuit for implementation in circuit boards with multiple processors is disclosed. The wake-up management circuit utilizes hardware resources to generate a wake-up signal for a processor in a low power mode when traffic intended for the processor is received by the wake-up management circuit. The wake-up management circuit is configured to generate a wake-up signal for a specific processor when address information in a data packet received by the wake-up management circuit indicates that the data packet is intended for the specific processor (e.g., the specific processor is the destination for the data packet).

Wake-up management circuit for multiple processors

Techniques to virtualize a physical hardware clock are described. The techniques may include utilizing a coefficients storage to store timestamp coefficient entries. When a timestamp request is received from a client, a selection circuit selects a timestamp coefficient entry from the coefficients storage. A compute circuit then computes a timestamp according to the client's virtualized clock based on the selected timestamp coefficient entry and a counter value of a counter that is driven by a physical clock signal.

Physical hardware clock virtualization

Techniques for low-latency packet processing are disclosed. A network device receives a first set of write transactions including a first set of data segments corresponding to a first DMA descriptor from a host. The network device receives a second set of write transactions including a second set of data segments corresponding to a second DMA descriptor from the host. The network device detects that the first set of data segments have been written. In response to detecting that the first set of data segments have been written, and prior to completely writing the second set of data segments and to receiving a packet notifier from the host, the network device processes the first DMA descriptor.

Low-latency packet processing for network device

An integrated circuit for distributing processing tasks includes a pre-selector circuit and a scheduler circuit. The pre-selector circuit is configured to receive a processing task, determine a category of the processing task, and select, from a set of task distribution techniques and based at least in part on the category of the processing task, a task distribution technique for distributing the processing task to a group of processing units. The scheduler circuit is configured to implement the selected task distribution technique to select, from the group of processing units, a target processing unit for performing the processing task.

Processing unit selection mechanism

Multiple independent endpoint devices can be emulated using a single system on chip (SoC) device. Such a SoC can have multiple cores that can emulate ports according to a specified protocol, such as the peripheral component interconnect express (PCIe) protocol useful for data communications. An emulation agent can manage various aspects of these emulated endpoint devices in software, including serving interrupts for relevant emulated devices according to a determined priority scheme. Interrupts can be registered for each device, and data structures allocated dynamically for a determined number and type(s) of PCIe endpoint devices to be emulated. Each PCIe core on the SoC can function as a separate PCIe endpoint device endpoint for communicating with one or more hosts or other such devices.

Multiple port emulation

Systems and methods are provided to reduce the latency in accessing an input/output (I/O) hardware register by software executing on a central processing unit (CPU). The hardware register is located in a controller coupled to the CPU via an I/O bus. The CPU software can send a command to the controller for execution. The controller can execute the command and update the hardware register to indicate that the command has been executed. The controller can write contents of the hardware register to a specified address in a CPU memory that is assigned by the CPU software. The CPU software can read the specified address to determine that the command has been executed instead of reading the hardware register on the I/O bus.

Input/output (I/O) register reflected in CPU memory

A resource request is received by a peripheral device from host processing logic. The resource request includes a requested resource size. The peripheral device allocates resource of the peripheral device in response to the resource request. A resource response is sent by the peripheral device to the host processing logic. The resource response includes a location of the allocated resource.

Dynamic resource management of network device

A clock disciplining scheme uses a pulse per second (PPS) signal that is distributed throughout a network to coordinate timing. In determining the time, jitter can occur due to latency between detection of the PPS signal and a software interrupt generated there from. This jitter affects the accuracy of the clock disciplining process. To eliminate the jitter, extra hardware is used to capture when the PPS signal occurred relative to a hardware clock counter associated with the clock disciplining software. In one embodiment, the extra hardware can be a sampling logic, which captures a state of a hardware clock counter upon PPS detection. In another embodiment, the extra hardware can initiate a counter that calculates a delay by the clock disciplining software in reading the hardware clock counter. The disciplining software can then subtract the calculated delay from a hardware clock counter to obtain the original PPS signal.

Clock synchronization in a network using a distributed pulse signal

Systems and methods are provided for highly accurate synchronization of machine instances in a distributed, hosted computing environment to a reference timekeeper. In addition to a general communication network accessible to machine instances, the distributed environment includes a second network dedicated to carrying time information, such as a pulse-per-second (PPS) signal to isolated timing hardware within host computing devices. The isolated timing hardware can use the PPS signal, along with a reference time, to set a hardware clock. The isolated timing hardware can further provide an interface to machine instances that enables the instances to read the time of the hardware clock. This configuration enables many instances can share access to a single reference timekeeper, thus synchronizing those instances to a much higher accuracy than in traditional network-based time protocols.

Highly accurate time information in hosted machine instances using dedicated timing network

To support different timestamp formats, for example, for different network protocols, an integrated circuit device is provided with a memory that is programmed with multiple instruction sets associated with multiple timestamp formats. Each of the instruction sets contains instructions to generate a timestamp according to a corresponding timestamp format. A compute circuit can generate a formatted timestamp by using a base timestamp input and executing an instruction set selected from the multiple instruction sets stored in the memory.

Packet timestamp format manipulation

Various embodiments of apparatuses and methods for multi-cast, multiple unicast, and unicast distribution of messages with time synchronized delivery are described. In some embodiments, the disclosed system and methods include a reference timekeeper providing a reference clock to one or more host computing devices. The one or more host computing devices host compute instances, and also contain respective isolated timing hardware outside the control of the compute instances. The isolated timing hardware of the one or more host computing devices then receive respective packets, and obtain the same time to deliver the respective packets. Each isolated timing hardware provides either the packet, or information to access the packet, to its respective destination compute instance subsequent to determining that the same specified time to deliver the packet has occurred. Thus, the respective packets are delivered near simultaneously to the one or more destination compute instances.

Distribution of messages with guaranteed or synchronized time of delivery

A packet header is received from a host and written to a header queue. A direct memory access (DMA) descriptor is received from the host and written to a packet descriptor queue. The DMA descriptor points to packet data in a host memory. The packet data is fetched from host memory and the packet header and the packet data are provided to a network interface.

Packet queueing for network device

Growing community of inventors

Tira, Israel

Said Bshara