Intel Corporation

Sai Vadlamani

Rahul Jain

Cheng Xu

Andrew James Brown

Kyu Oh Lee

Junnan Zhao

Lauren Ashley Link

Ji Yong Park

Prithwish Chatterjee

Seo Young Kim

Kyu-Oh Lee

Sheng C Li

Amruthavalli Pallavi Alur

Siddharth K Alur

Rahul N Manepalli

Robert Alan May

Wei-Lun Kane Jen

Vipul V Mehta

Sri Chaitra J Chavali

Ashish Dhall

Brandon C Marin

Chong Zhang

Ying Wang

Srinivas V Pietambaram

Omkar G Karhade

Sri Ranga Sai Boyapati

Tarek A Ibrahim

Aleksandar Aleksov

Telesphor Kamgaing

Kristof Darmawikarta

Nitin A Deshpande

Zhichao Zhang

Jeremy D Ecton

Gang Duan

Hiroki Tanaka

Xiaoqian Li

Bharat P Penmecha

Bai Nie

Darko Grujicic

Marcel Arlan Wall

Benjamin Duong

Tolga Acikalin

Jonathan Rosch

Haobo Chen

Divya Pratap

Liwei Cheng

Michael Garelick

Omkar Karhade

Nitin Deshpande

Embodiments disclosed herein include optical systems with Faraday rotators in order to enhance efficiency. In an embodiment, a photonics package comprises an interposer and a patch over the interposer. In an embodiment, the patch overhangs an edge of the interposer. In an embodiment, the photonics package further comprises a photonics die on the patch and a Faraday rotator passing through a thickness of the patch. In an embodiment, the Faraday rotator is below the photonics die.

Faraday rotator interconnect as a through-via configuration in a patch architecture

An electronic substrate may be fabricated having a core comprising a laminate including a metal layer between a first insulator layer and a second insulator layer, a metal via through the core, and metallization features on a first side and a second side of the core, wherein first ones of the metallization features are embedded within dielectric material on the first side of the core, and wherein a sidewall of the dielectric material and of the first insulator layer defines a recess over an area of the metal layer. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.

Electronic substrate core having an embedded laser stop to control depth of an ultra-deep cavity

Disclosed herein are microelectronic structures including glass cores, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a glass core having through-glass vias (TGVs) therein; a metallization region at a first face of the glass core, wherein a conductive pathway in the first metallization region is conductively coupled to at least one of the TGVs; a bridge component in the metallization region; a first conductive contact at a face of the metallization region, wherein the first conductive contact is conductively coupled to the conductive pathway; and a second conductive contact at the face of the metallization region, wherein the second conductive contact is conductively coupled to the bridge component.

Microelectronic structures including glass cores

An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

Package with underfill containment barrier

Embodiments include an inductor that comprises an inductor trace and a magnetic body surrounding the inductor trace. In an embodiment, the magnetic body comprises a first step surface and a second step surface. Additional embodiments include an inductor that includes a barrier layer. In an embodiment, an inductor trace is formed over a first surface of the barrier layer. Embodiments include a first magnetic body over the inductor trace and the first surface of the barrier layer, and a second magnetic body over a second surface of the barrier layer opposite the first surface. In an embodiment, a width of the second magnetic body is greater than a width of the first magnetic body.

Methods to selectively embed magnetic materials in substrate and corresponding structures

An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.

Electronic substrates having embedded inductors

Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.

Substrate assembly with encapsulated magnetic feature

A coreless semiconductor package comprises a plurality of horizontal layers of dielectric material. A magnetic inductor is situated at least partly in a first group of the plurality of layers. A plated laser stop is formed to protect the magnetic inductor against subsequent acidic processes. An EMIB is situated above the magnetic inductor within a second group of the plurality of layers. Vias and interconnections are configured within the horizontal layers to connect a die of the EMIB to other circuitry. A first level interconnect is formed on the top side of the package to connect to the interconnections. BGA pockets and BGA pads are formed on the bottom side of the package. In a second embodiment a polymer film is used as additional protection against subsequent acidic processes. The magnetic inductor comprises a plurality of copper traces encapsulated in magnetic material.

Coreless organic packages with embedded die and magnetic inductor structures

Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.

Methods of embedding magnetic structures in substrates

Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.

Methods to embed magnetic material as first layer on coreless substrates and corresponding structures

Embodiments herein relate to systems, apparatuses, processing, and techniques related to patterning one or more sides of a thin film capacitor (TFC) sheet, where the TFC sheet has a first side and a second side opposite the first side. The first side and the second side of the TFC sheet are metal and are separated by a dielectric layer, and the patterned TFC sheet is to provide at least one of a capacitor or a routing feature on a first side of a substrate that has the first side and a second side opposite the first side.

Patterning of thin film capacitors in organic substrate packages

A substrate for an integrated circuit package, the substrate comprising a dielectric, at least one conductor plane within the dielectric, and a planar magnetic structure comprising an organic magnetic laminate embedded within the dielectric, wherein the planar magnetic structure is integrated within the at least one conductor plane.

Release layer-assisted selective embedding of magnetic material in cored and coreless organic substrates

Disclosed herein are cavity structures in integrated circuit (IC) package supports, as well as related methods and apparatuses. For example, in some embodiments, an IC package support may include: a cavity in a dielectric material, wherein the cavity has a bottom and sidewalls; conductive contacts at the bottom of the cavity, wherein the conductive contacts include a first material; a first peripheral material outside the cavity, wherein the first peripheral material is at the sidewalls of the cavity and proximate to the bottom of the cavity, and the first peripheral material includes the first material; and a second peripheral material outside the cavity, wherein the second peripheral material is at the sidewalls of the cavity and on the first peripheral material, and the second peripheral material is different than the first peripheral material.

Cavity structures in integrated circuit package supports

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Chandler, AZ, United States of America

Sai Vadlamani