Cypress Semiconductor Corporation

Sai Prashanth Dhanraj

Andrew J Walker

Helmut Puchner

Kevin Jang

Roger J Bettman

Sungkwon Lee

Dung Ho

Leo F Luquette, Jr

Iman Rezanezhad Gatabi

An ESD device that includes a gate and an n-drain region isolated from the gate and formed at least partially within an n-well region, which in turn is formed at least partially within a deep n-well region. The doping levels of the n-drain region, the n-well region and the deep n-well region are in a descending order. The ESD device has trigger and holding voltages, above the operation voltage of its protected circuit, which are layout-configurable by altering the distance between the n-drain and a side edge of the n-well region.

ESD clamp with a layout-alterable trigger voltage and a holding voltage above the supply voltage

A circuit with electrostatic discharge protection is described. In one case, the circuit includes trigger device configured to protect a component connected to a node of the circuit during an electrostatic discharge event, the trigger device includes an isolation structure interposed between a gate oxide layer and an extended drain region. A portion of the extended drain region proximate the isolation structure is substantially metal-free.

Circuit with electrostatic discharge protection

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San Jose, CA, United States of America

Sai Prashanth Dhanraj