Advanced Micro Devices Corporation

Sai-Keung Lee

Robert D Norman

Om P Agrawal

Kou-Su Chen

A programmable logic device is disclosed having a delay line macrocell with programmably selectable taps feeding inputs to a programmable logic circuit. The delay line taps may feed the programmable logic circuit through logic circuit driving circuitry, which performs a certain amount of prepossessing on the tap signals before being provided to the programmable logic circuit. Outputs of the programmable logic circuit, which may be a programmable AND array followed by a fixed OR array, are provided to the edge-triggered inputs of dual set/reset flip flops. Other outputs of the programmable logic circuit are selectable as inputs to the delay line.

Precision timing control programmable logic device

A simple edge-triggered flip-flop is provided that does not require a clock or a master-slave structure. In some embodiments, the flip-flop has multiple set, reset and/or trigger (T) inputs.

Edge-triggered flip-flop

An apparatus for a signal processing system connected to a power supply having an output level and receiving a clock signal, that is responsive to the output level of the power supply, generates control signals for use as interrupt signals, reset signals and warning signals to the system. The apparatus comprises a detector for generating an undervoltage signal while the output level of the power supply is below a prespecified threshold; a circuit for supplying a programmable signal indicating a programmable threshold; a comparator connected to the power supply and receiving the programmable signal, for generating a voltage threshold signal while the output level is below the programmable threshold; and a programmable logic circuit. The programmable logic circuit receives general purpose inputs, the clock, the undervoltage signal and the low voltage signal, and generates the control signals. Using the invention, designers can easily create a wide variety of individual and sequential control signals which can be generated during power-up and power glitches, in response to externally forced signals, or during undervoltage occurrences.

Programmable power supply level detection and initialization circuitry

A typical peripheral system includes a control path and a data path along with a peripheral controller that processes different type of instructions for control and data paths. Since control and data paths are not independent of each other, it is necessary to either combine these two types of instructions in a single instruction or execute these two types of instructions in a prescribed manner so that a control path instruction can be executed while a data path instruction is being executed. The data path instructions (which may also be called event-count instructions) includes serialization and deserialization of data and other information such as ECC, and typically have lengths of events, or fields, typically in words and bytes associated with them. Control instructions (which may also be referred to as nonevent-count instructions) include setting of tag patterns, branching or jumping or typically have no fields of data associated with them. In the present invention, the peripheral controller can execute nonevent-count instructions before the end of a previous event-count instruction, and when a next event-count instruction is fetched, it must wait for the end of a previous event-count instruction before the new event-count instruction can be executed. In this way, all nonevent-count instructions between two event-count instructions, for both contiguous and noncontiguous event-count instructions, can be executed in sequence, and the timing dependencies between these two different types of instructions can be maintained.

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Milpitas, CA, United States of America

Sai-Keung Lee