Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Sai-Hooi Yeong

Yu-Ming Lin

Bo-Feng Young

Chi On Chui

Han-Jong Chia

Sheng-Chen Wang

Chih-Yu Chang

Kai-Hsuan Lee

Meng-Han Lin

Yen-Ming Chen

Feng-Cheng Yang

Chun-Chieh Lu

Chih-Hao Wang

Chia-Ta Yu

Chenchen Jacob Wang

Kuan-Lun Cheng

Chi-On Chui

Mauricio Manfrini

Chun-Yen Peng

Bo-Yu Lai

Te-Yang Lai

Cheng-Yu Yang

Yih Wang

Ziwei Fang

Chao-I Wu

Ching-Wei Tsai

Tsung-Yao Wen

Cheng-Ming Lin

Jui-Yao Lai

Chung-Te Lin

Yen-Chieh Huang

Chien-Ning Yao

Shih-Lien Linus Lu

Huang-Lin Chao

Chia-En Huang

Pei-Yu Wang

Wei-Yuan Lu

Chien Ning Yao

Hai-Ching Chen

Yi-Ching Liu

Chi-Hsing Hsu

Min Cao

Georgios Vellianitis

Tzu-Chiang Chen

I-Sheng Chen

Zhiqiang Wu

Chih-Hao Yu

Tsung-Chieh Hsiao

Nuo Xu

Ya-Yun Cheng

Po-Ting Lin

Jhon-Jhy Liaw

Tien-I Bao

Wei-Yang Lee

Hung-Li Chiang

Chao-Ching Cheng

Kuo-Hua Pan

Sheng-Chih Lai

Ta-Chun Lin

Chien-I Kuo

Min-Chang Liang

Bo-Cyuan Lu

Wei-Ken Lin

Wen-Kai Lin

Shih-Syuan Huang

Ru-Gun Liu

Cheng-Hsien Wu

Chih-Sheng Chang

Sung-Li Wang

Chun-Hsiung Lin

Hsueh-Chang Sung

Hou-Yu Chen

Yung-Sung Yen

Marcus Johannes Henricus Van Dal

Yu-Xuan Huang

Yen-Ting Chen

Yih-Ann Lin

Chih-Chieh Yeh

Yu-Lin Yang

Li-Li Su

Jyh-Cherng Sheu

Tzer-Min Shen

Jeng-Ya David Yeh

Chun-Hsiang Fan

Yi-Bo Liao

Kuo-Chang Chiang

Chia-en Huang

Wei-Han Fan

Chun-An Lin

Kuo-Cheng Ching

Syun-Ming Jang Jang

Wen-Hsing Hsieh

Han-Ting Tsai

Ken-Ichi Goto

Jin-Aun Ng

Kuan-lun Cheng

Yi-Fang Pai

Ying-Chih Chen

A memory cell includes a read word line extending in a first direction, a write transistor, and a read transistor coupled to the write transistor. The read transistor includes a ferroelectric layer, a drain terminal of the read transistor directly connected to the read word line, and a source terminal of the read transistor coupled to a first node. The write transistor is configured to adjust a polarization state of the read transistor, the polarization state corresponding to a stored data value of the memory cell.

Memory cell and method of operating the same

A semiconductor device includes a semiconductor substrate, first and second stack units disposed over the semiconductor substrate, and a feature disposed between the first and second stack units. Each of the first and second stack units includes at least one stack that includes a conductive film and a dielectric film stacked on each other. The feature includes a plurality of repeating units and a plurality of separators disposed to alternate with the repeating units. Each of the repeating units includes an inner portion including a pair of conductive pillars, and an outer portion including a memory film and a channel film. A method for manufacturing the semiconductor device is also disclosed.

Semiconductor memory device and method for manufacturing the same

A method for forming a semiconductor arrangement comprises forming a fin over a semiconductor layer. A gate structure is formed over a first portion of the fin. A second portion of the fin adjacent to the first portion of the fin and a portion of the semiconductor layer below the second portion of the fin are removed to define a recess. A stress-inducing material is formed in the recess. A first semiconductor material is formed in the recess over the stress-inducing material. The first semiconductor material is different than the stress-inducing material.

Semiconductor arrangement and method of manufacture

The present disclosure, in some embodiments, relates to a memory device. In some embodiments, the memory device has a substrate and a lower interconnect metal line disposed over the substrate. The memory device also has a selector channel disposed over the lower interconnect metal line and a selector gate electrode wrapping around a sidewall of the selector channel and separating from the selector channel by a selector gate dielectric. The memory device also has a memory cell disposed over and electrically connected to the selector channel and an upper interconnect metal line disposed over the memory cell. By placing the selector within the back-end interconnect structure, front-end space is saved, and more integration flexibility is provided.

Back-end-of-line selector for memory device

An improved memory cell architecture including a nanostructure field-effect transistor (nano-FET) and a horizontal capacitor extending at least partially under the nano-FET and methods of forming the same are disclosed. In an embodiment, semiconductor device includes a channel structure over a semiconductor substrate; a gate structure encircling the channel structure; a first source/drain region adjacent the gate structure; and a capacitor adjacent the first source/drain region, the capacitor extending under the first source/drain region and the gate structure in a cross-sectional view.

Memory cell and method

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin formed on a substrate; and a gate structure disposed over a channel region of the semiconductor fin, the gate structure including a gate dielectric layer and a gate electrode, wherein the gate dielectric layer includes a bottom portion and a side portion, and the gate electrode is separated from the side portion of the gate dielectric layer by a first air gap.

FinFET structure with airgap and method of forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first nanostructure over the substrate. The semiconductor device structure also includes a gate stack over the substrate and surrounding the first nanostructure and a first source/drain layer surrounding the first nanostructure and adjacent to the gate stack. The semiconductor device structure further includes a contact structure surrounding the first source/drain layer. A first portion of the contact structure is between the first nanostructure and the substrate, and the first portion of the contact structure has a first curved top surface facing the first nanostructure.

Semiconductor device structure with nanostructure

A method of writing data to a memory array of three-terminal memory cells includes simultaneously programming a first subset of memory cells in a first column of the memory array to a first logic level by activating a first select line of the first column and a first bit line of the first column, and simultaneously programming a second subset of memory cells in the first column to the first logic level by activating the first select line and a second bit line of the first column.

Memory circuit and write method

A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.

Flexible merge scheme for source/drain epitaxy regions

A semiconductor device includes a first device over a substrate, wherein the first device includes a gate stack including a gate electrode material; a source/drain region in the substrate adjacent the gate stack; a first isolation region surrounding the gate stack; a gate contact over and contacting the gate stack, wherein the gate contact includes a gate contact material; and a second isolation region surrounding the gate contact; and a second device over the substrate, wherein the second device includes a first parallel capacitor including first electrodes, wherein the first electrodes include the gate electrode material, wherein the first isolation region separates the first electrodes; and a second parallel capacitor over the first parallel capacitor, wherein the second parallel capacitor includes second electrodes connected to the first electrodes, wherein the second electrodes include the gate contact material, wherein adjacent second electrodes are separated by the second isolation region.

Semiconductor device and method for forming capacitor structure

An embodiment is a semiconductor device including a first channel region over a semiconductor substrate, a second channel region over the first channel region, a first gate stack over the semiconductor substrate and surrounding the first channel region and the second channel region, a first inner spacer extending from the first channel region to the second channel region and along a sidewall of the first gate stack, a second inner spacer extending from the first channel region to the second channel region and along a sidewall of the first inner spacer, the second inner spacer having a different material composition than the first inner spacer, and a first source/drain region adjacent the first channel region, the second channel region, and the second inner spacer, the first and second inner spacers being between the first gate stack and the first source/drain region.

Semiconductor device and method

Semiconductor devices and methods of manufacturing are presented wherein a gate dielectric is treated within an analog region of a semiconductor substrate. The gate dielectric may be treated with a plasma exposure and/or an annealing process in order to form a recovered region of the gate dielectric. A separate gate dielectric is formed within a logic region of the semiconductor substrate, and a first gate electrode and second gate electrode are formed over the gate dielectrics.

Semiconductor device and method of manufacturing

A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material.

Three-dimensional stackable ferroelectric random access memory devices and methods of forming

Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. In addition, the nanostructures includes channel regions and source/drain regions. The semiconductor structure further includes a gate structure vertically sandwiched the channel regions of the nanostructures and a contact wrapping around and vertically sandwiched between the source/drain regions of the nanostructures.

Semiconductor structure with extended contact structure

A method includes depositing an interlayer dielectric (ILD) over a source/drain region, implanting impurities into a portion of the ILD, recessing the portion of the ILD to form a trench, forming spacers on sidewalls of the trench, the spacers including a spacer material, forming a source/drain contact in the trench and removing the spacers and the portion of the ILD with an etching process to form an air-gap, the air-gap disposed under and along sidewalls of the source/drain contact, where the etching process selectively etches the spacer material and the impurity.

Fin field-effect transistor device and method

Growing community of inventors

Zhubei, Taiwan

Sai-Hooi Yeong