Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Sai-Hooi Yeong

Yu-Ming Lin

Bo-Feng Young

Chi On Chui

Han-Jong Chia

Sheng-Chen Wang

Chih-Yu Chang

Kai-Hsuan Lee

Meng-Han Lin

Yen-Ming Chen

Feng-Cheng Yang

Chun-Chieh Lu

Chia-Ta Yu

Chih-Hao Wang

Chenchen Jacob Wang

Kuan-Lun Cheng

Chi-On Chui

Mauricio Manfrini

Chun-Yen Peng

Bo-Yu Lai

Te-Yang Lai

Yih Wang

Ziwei Fang

Cheng-Yu Yang

Chao-I Wu

Tsung-Yao Wen

Ching-Wei Tsai

Cheng-Ming Lin

Jui-Yao Lai

Chung-Te Lin

Yen-Chieh Huang

Chien-Ning Yao

Huang-Lin Chao

Shih-Lien Linus Lu

Chia-En Huang

Wei-Yuan Lu

Hai-Ching Chen

Yi-Ching Liu

Pei-Yu Wang

Chi-Hsing Hsu

Chien Ning Yao

Min Cao

Georgios Vellianitis

Tzu-Chiang Chen

I-Sheng Chen

Zhiqiang Wu

Chih-Hao Yu

Tsung-Chieh Hsiao

Nuo Xu

Ya-Yun Cheng

Po-Ting Lin

Jhon-Jhy Liaw

Tien-I Bao

Hung-Li Chiang

Chao-Ching Cheng

Kuo-Hua Pan

Sheng-Chih Lai

Ta-Chun Lin

Min-Chang Liang

Chien-I Kuo

Bo-Cyuan Lu

Wei-Ken Lin

Wen-Kai Lin

Shih-Syuan Huang

Ru-Gun Liu

Wei-Yang Lee

Cheng-Hsien Wu

Chih-Sheng Chang

Chun-Hsiung Lin

Sung-Li Wang

Hsueh-Chang Sung

Hou-Yu Chen

Yung-Sung Yen

Marcus Johannes Henricus Van Dal

Yen-Ting Chen

Yu-Xuan Huang

Yih-Ann Lin

Chih-Chieh Yeh

Yu-Lin Yang

Li-Li Su

Jyh-Cherng Sheu

Tzer-Min Shen

Jeng-Ya David Yeh

Chun-Hsiang Fan

Yi-Bo Liao

Kuo-Chang Chiang

Wei-Han Fan

Chia-en Huang

Chun-An Lin

Kuo-Cheng Ching

Syun-Ming Jang Jang

Wen-Hsing Hsieh

Han-Ting Tsai

Ken-Ichi Goto

Jin-Aun Ng

Yi-Fang Pai

Kuan-lun Cheng

Ying-Chih Chen

A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.

Flexible merge scheme for source/drain epitaxy regions

A semiconductor device includes a first device over a substrate, wherein the first device includes a gate stack including a gate electrode material; a source/drain region in the substrate adjacent the gate stack; a first isolation region surrounding the gate stack; a gate contact over and contacting the gate stack, wherein the gate contact includes a gate contact material; and a second isolation region surrounding the gate contact; and a second device over the substrate, wherein the second device includes a first parallel capacitor including first electrodes, wherein the first electrodes include the gate electrode material, wherein the first isolation region separates the first electrodes; and a second parallel capacitor over the first parallel capacitor, wherein the second parallel capacitor includes second electrodes connected to the first electrodes, wherein the second electrodes include the gate contact material, wherein adjacent second electrodes are separated by the second isolation region.

Semiconductor device and method for forming capacitor structure

An embodiment is a semiconductor device including a first channel region over a semiconductor substrate, a second channel region over the first channel region, a first gate stack over the semiconductor substrate and surrounding the first channel region and the second channel region, a first inner spacer extending from the first channel region to the second channel region and along a sidewall of the first gate stack, a second inner spacer extending from the first channel region to the second channel region and along a sidewall of the first inner spacer, the second inner spacer having a different material composition than the first inner spacer, and a first source/drain region adjacent the first channel region, the second channel region, and the second inner spacer, the first and second inner spacers being between the first gate stack and the first source/drain region.

Semiconductor device and method

Semiconductor devices and methods of manufacturing are presented wherein a gate dielectric is treated within an analog region of a semiconductor substrate. The gate dielectric may be treated with a plasma exposure and/or an annealing process in order to form a recovered region of the gate dielectric. A separate gate dielectric is formed within a logic region of the semiconductor substrate, and a first gate electrode and second gate electrode are formed over the gate dielectrics.

Semiconductor device and method of manufacturing

A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material.

Three-dimensional stackable ferroelectric random access memory devices and methods of forming

Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. In addition, the nanostructures includes channel regions and source/drain regions. The semiconductor structure further includes a gate structure vertically sandwiched the channel regions of the nanostructures and a contact wrapping around and vertically sandwiched between the source/drain regions of the nanostructures.

Semiconductor structure with extended contact structure

A method includes depositing an interlayer dielectric (ILD) over a source/drain region, implanting impurities into a portion of the ILD, recessing the portion of the ILD to form a trench, forming spacers on sidewalls of the trench, the spacers including a spacer material, forming a source/drain contact in the trench and removing the spacers and the portion of the ILD with an etching process to form an air-gap, the air-gap disposed under and along sidewalls of the source/drain contact, where the etching process selectively etches the spacer material and the impurity.

Fin field-effect transistor device and method

A semiconductor device structure is provided. The semiconductor device structure includes a transistor which includes a source/drain feature adjoining an active region, and a gate stack over the active region. The semiconductor device structure further includes a capacitor above the transistor, the capacitor including a bottom electrode layer on the gate stack and a ferroelectric layer on the bottom electrode layer. The ferroelectric layer is made of a Hf-based dielectric material. The semiconductor device structure further includes gate spacer layers surrounding the gate stack, the bottom electrode layer and the ferroelectric layer.

Semiconductor device structure and method for forming the same

A thin film transistor may be manufactured by forming a gate electrode in an insulating layer over a substrate, forming a gate dielectric over the gate electrode and the insulating layer, forming an active layer over the gate electrode, and forming a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. A surface oxygen concentration may be increased in at least one of the gate dielectric and the active layer by introducing oxygen atoms into a surface region of a respective one of the gate dielectric and the active layer.

Thin film transistor including a compositionally- graded gate dielectric and methods for forming the same

A method for fabricating a three-dimensional memories is provided. A stack with multiple levels is formed, and each of the levels includes an isolation layer, a metal layer, and a semiconductor layer between the isolation layer and the metal layer. A first trench and a plurality of second trenches are formed along each parallel line in the stack of the levels. The isolation layers and the metal layers in the parallel lines are removed through the first trench and the second trenches, so as to expose the semiconductor layers in the parallel line. A plurality of memory cells are formed in the parallel lines of the levels. In each of the levels, each of the memory cells includes a transistor and a channel of the transistor is formed by the semiconductor layer in the parallel line.

Method for fabricating three-dimensional memory

In a method of manufacturing a semiconductor device, a first layer containing an amorphous first material is formed by a deposition process over a semiconductor layer. A second layer containing a metal second material is formed over the first layer. A thermal process is performed to form an alloy layer of the amorphous first material and the metal second material.

Semiconductor device having a uniform and thin silicide layer on an epitaxial source/drain structure

One aspect of this description relates to a memory array. In some embodiments, the memory array includes a first memory cell coupled between a first local select line and a first local bit line, a second memory cell coupled between a second local select line and a second local bit line, a first switch coupled to a global bit line, a second switch coupled between the first local bit line and the first switch, and a third switch coupled between the second local select line and the first switch.

Using embedded switches for reducing capacitive loading on a memory system

A method (of writing to a ferroelectric field-effect transistor (FeFET) configured as a 2-bit storage device that stores two bits, wherein the FeFET includes a first source/drain (S/D) terminal, a second S/D terminal, a gate terminal and a ferroelectric layer, a second bit being at a first end of the ferroelectric layer, the first end being proximal to the first S/D terminal) includes: setting the second bit to a logical 1 value, the setting a second bit including applying a gate voltage to the gate terminal, and applying a first source/drain voltage to the second S/D terminal; and wherein the first source/drain voltage is lower than the gate voltage.

Method of writing to or erasing multi-bit memory storage device

Various embodiments of the present disclosure provide a memory device and methods of forming the same. In one embodiment, a memory device is provided. The memory device includes a gate electrode disposed in an insulating material layer, a ferroelectric dielectric layer disposed over the gate electrode, a metal oxide semiconductor layer disposed over the ferroelectric dielectric layer, a source feature disposed over the metal oxide semiconductor layer, wherein the source feature has a first dimension, and a source extension. The source extension includes a first portion disposed over the source feature, wherein the first portion has a second dimension that is greater than the first dimension. The source extension also includes a second portion extending downwardly from the first portion to an elevation that is lower than a top surface of the source feature.

Ferroelectric device and methods of forming the same

A ferroelectric memory device includes a multi-layer stack, a channel layer and a III-V based ferroelectric layer. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers of the multi-layer stack. The III-V based ferroelectric layer is disposed between the channel layer and the multi-layer stack, and includes at least one element selected from Group III elements, at least one element selected from Group V elements, and at least one element selected from transition metal elements.

Ferroelectric memory device and method of forming the same

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Zhubei, Taiwan

Sai-Hooi Yeong