Texas Instruments Corporation

Sai Aditya Krishnaswamy Nurani

Visvesvaraya Appala Pentakota

Shagun Dusad

Prasanth K

Joseph Palackal Mathew

Jagannathan Venkataraman

Eeshan Miglani

Neeraj Shrivastava

Arun Kumar Mohan

Kartik Goel

A voltage-to-delay converter converts input signals into delay signals, and includes: a first stage for receiving the input signals and for generating intermediate output signals, wherein timing of the intermediate output signals corresponds to voltages of the input signals, and wherein the first stage has a voltage source for providing a rail-to-rail voltage; and a second stage for receiving the intermediate output signals and for generating rail-to-rail output signals, wherein timing of the rail-to-rail output signals corresponds to the timing of the intermediate output signals, and wherein voltage of the rail-to-rail output signals corresponds to the rail-to-rail voltage. A voltage-to-delay converter block is also described. A circuit for receiving differential input signals, generating corresponding output signals, and removing common mode signals from the output signals is also described.

Differential voltage-to-delay converter with improved CMRR

An example sample-and-hold circuit includes a first and second input resistors, each having first and second terminals; first and second transistors coupled in series between the second terminals of the first and second input resistors; and third and fourth input resistors, each having first and second terminals; and third and fourth transistors coupled in series between the second terminals of the third and fourth input resistors. A first capacitor is coupled between the first and second transistors and a second capacitor is coupled between the third and fourth transistors. The control terminals of the first and third transistors are coupled together, and the control terminals of the second and fourth transistors are coupled together.

Current-based track and hold circuit

A sample-and-hold circuit includes a first input resistor, a first transistor, a first capacitor, a second resistor, and a first current source device. A first current terminal of the first transistor is coupled to the first input resistor. A first terminal of the first capacitor is coupled to the second current terminal of the first transistor at a first output node. A first terminal of the second resistor is coupled to the second terminal of the first transistor at the first output node. The first current source device is coupled the first input resistor and to the first current terminal of the first transistor.

A top-plate sampling analog-to-digital converter (ADC) circuit includes a first ADC stage and a residue amplifier coupled to the first ADC stage. The residue amplifier comprises a first transistor with a control terminal, a first current terminal, and a second current terminal. The residue amplifier also comprises a second transistor with a control terminal, a first current terminal, and a second current terminal. The residue amplifier also comprises a linearity adjustment circuit coupled to a second current terminal of at least one of the first transistor and the second transistor. The linearity adjustment circuit comprises at least one switch that changes its state as a function of an input sampling phase and a gain phase of the residue amplifier.

Top plate sampling analog-to-digital converter (ADC) with residue amplifier non-linearity reduction

A pipelined analog-to-digital converter (ADC) circuit includes a first ADC stage and a residue stage coupled to the first ADC stage. The residue stage includes a dynamic integrator configured to provide transconductance, wherein the dynamic integrator includes a boost circuit configured to boost an output impedance of the transconductance.

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Hyderabad Telangana, India

Sai Aditya Krishnaswamy Nurani