Taiwan Semiconductor Manufacturing Comp. Ltd.

Headway Technologies, Incorporated

Applied Materials, Inc.

Sahil Patel

Yu-Jen Wang

Vignesh Sundar

Dongna Shen

Ru-Ying Tong

Guenole Jan

Huanlong Liu

Yi Yang

Luc Thomas

Jian Zhu

Yuan-Jen Lee

Jodi Mari Iwata

Po-Kang Wang

Mahendra Pakala

Chando Park

Lin Xue

Jaesoo Ahn

Rongjun Wang

Yixiong Yang

Yu Lei

Tom Zhong

Chentsau Chris Ying

Huixiong Dai

Christopher S Ngai

Jesmin Haq

Wenhui Wang

Yi Xu

Zhongjian Teng

Jong Mun Kim

Wei Lei

Minrui Yu

Aixi Zhang

Shiyu Yue

Xingyao Gao

Ju Hyun Oh

Xiangjin Xie

Xiaodong Wang

Kevin Kashefi

Tsung-Han Yang

Cong Trinh

Chih-Hsun Hsu

Jiajie Cen

Zhimin Qi

Abulaiti Hairisha

A method of pre-cleaning in a semiconductor structure includes performing a plasma pre-treatment process to remove impurities from a surface of a semiconductor structure comprising a metal layer and a dielectric layer, performing a selective etch process to remove molybdenum oxide from a surface of the metal layer, the selective etch process comprising soaking the semiconductor structure in a precursor including molybdenum chloride (MoCl, MoCl) at a temperature of between 250° C. and 350° C., and performing a post-treatment process to remove chlorine residues and by-products of the selective etch process on the surface of the semiconductor structure.

Metal oxide preclean for bottom-up gapfill in MEOL and BEOL

A method of selective metal removal via gradient oxidation for a gap-fill includes performing process cycles, each process cycle including placing a wafer having a semiconductor structure thereon into a first processing station, the semiconductor structure including a dielectric layer patterned with a feature formed therein and a seed layer formed on sidewalls and a bottom surface of the feature and a top surface of the dielectric layer, performing a reduction process on the wafer in the first processing station, performing a gradient oxidation process on the wafer in the second processing station, performing a gradient etch process on the wafer in the third processing station, and performing the gradient etch process on the wafer in the fourth processing station, wherein the first, second, third, and fourth processing stations are located in an interior volume of a processing chamber.

One chamber multi-station selective metal removal

A seed layer stack with a uniform top surface having a peak to peak roughness of 0.5 nm is formed by sputter depositing an amorphous layer on a smoothing layer such as Mg where the latter has a resputtering rate 2 to 30× that of the amorphous layer. The uppermost seed layer is NiW, NiMo, or one or more of NiCr, NiFeCr, and Hf while the bottommost seed layer is one or more of Ta, TaN, Zr, ZrN, Nb, NbN, Mo, MON, TIN, W, WN, and Ru. Accordingly, perpendicular magnetic anisotropy in an overlying magnetic layer is substantially maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The amorphous seed layer is SiN, TaN, or CoFeM where M is B or another element with a content that makes CoFeM amorphous as deposited.

Multilayer structure for reducing film roughness in magnetic devices

A plurality of conductive via connections are fabricated on a substrate located at positions where MTJ devices are to be fabricated, wherein a width of each of the conductive via connections is smaller than or equivalent to a width of the MTJ devices. The conductive via connections are surrounded with a dielectric layer having a height sufficient to ensure that at the end of a main MTJ etch, an etch front remains in the dielectric layer surrounding the conductive via connections. Thereafter, a MTJ film stack is deposited on the plurality of conductive via connections surrounded by the dielectric layer. The MTJ film stack is etched using an ion beam etch process (IBE), etching through the MTJ film stack and into the dielectric layer surrounding the conductive via connections to form the MTJ devices wherein by etching into the dielectric layer, re-deposition on sidewalls of the MTJ devices is insulating.

Etching and encapsulation scheme for magnetic tunnel junction fabrication

Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.

Spin-orbit torque MRAM structure and manufacture thereof

A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a NO:silane flow rate ratio of at least 1:1 but less than 15:1. A NO plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.

Silicon oxynitride based encapsulation layer for magnetic tunnel junctions

A dual magnetic tunnel junction (DMTJ) is disclosed with a PL/TB/free layer/TB/PL/capping layer configuration wherein a first tunnel barrier (TB) has a substantially lower resistance x area (RA) product than RAfor an overlying second tunnel barrier (TB) to provide an acceptable net magnetoresistive ratio (DRR). Moreover, magnetizations in first and second pinned layers, PLand PL, respectively, are aligned antiparallel to enable a lower critical switching current than when in a parallel alignment. An oxide capping layer having a RAis formed on PLto provide higher PLstability. The condition RA<RAand RA<RAis achieved when TBand the oxide capping layer have one or both of a smaller thickness and a lower oxidation state than TB, are comprised of conductive (metal) channels in a metal oxide or metal oxynitride matrix, or are comprised of a doped metal oxide or doped metal oxynitride layer.

Dual magnetic tunnel junction (DMTJ) stack design

A fabrication process for an STT MTJ MRAM device includes steps of cooling the device at individual or at multiple stages in its fabrication. The cooling process, which may be equally well applied during the fabrication of other multi-layered devices, is demonstrated to produce an operational device that is more resistant to adverse thermal effects during operation that would normally cause a similar device not so fabricated to lose stored data and otherwise fail to operate properly.

Cooling for PMA (perpendicular magnetic anisotropy) enhancement of STT-MRAM (spin-torque transfer-magnetic random access memory) devices

A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode. A top electrode is provided on the MTJ stack. The top electrode is patterned. Thereafter, the MTJ stack not covered by the patterned top electrode is oxidized or nitridized. Then, the MTJ stack is patterned to form a MTJ device wherein any sidewall re-deposition formed on sidewalls of the MTJ device is non-conductive and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.

Post treatment to reduce shunting devices for physical etching process

A magnetic tunnel junction (MTJ) is disclosed wherein a free layer (FL) interfaces with a first metal oxide (Mox) layer and second metal oxide (tunnel barrier) to produce perpendicular magnetic anisotropy (PMA) in the FL. In some embodiments, conductive metal channels made of a noble metal are formed in the Mox that is MgO to reduce parasitic resistance. In a second embodiment, a discontinuous MgO layer with a plurality of islands is formed as the Mox layer and a non-magnetic hard mask layer is deposited to fill spaces between adjacent islands and form shorting pathways through the Mox. In another embodiment, end portions between the sides of a center Mox portion and the MTJ sidewall are reduced to form shorting pathways by depositing a reducing metal layer on Mox sidewalls, or performing a reduction process with forming gas, H, or a reducing species.

Low resistance MgO capping layer for perpendicularly magnetized magnetic tunnel junctions

A MgO layer is formed using a process flow wherein a Mg layer is deposited at a temperature &#x3c;200&#xb0; C. on a substrate, and then an anneal between 200&#xb0; C. and 900&#xb0; C., and preferably from 200&#xb0; C. and 400&#xb0; C., is performed so that a Mg vapor pressure &#x3e;10Torr is reached and a substantial portion of the Mg layer sublimes and leaves a Mg monolayer. After an oxidation between &#x2212;223&#xb0; C. and 900&#xb0; C., a MgO monolayer is produced where the Mg:O ratio is exactly 1:1 thereby avoiding underoxidized or overoxidized states associated with film defects. The process flow may be repeated one or more times to yield a desired thickness and resistance&#xd7;area value when the MgO is a tunnel barrier or Hk enhancing layer. Moreover, a doping element (M) may be added during Mg deposition to modify the conductivity and band structure in the resulting MgMO layer.

Monolayer-by-monolayer growth of MgO layers using mg sublimation and oxidation

A film stack for a magnetic tunnel comprises a substrate, a magnetic reference layer disposed over the substrate, and a tunnel barrier layer disposed over the magnetic reference layer. The film stack further comprises a magnetic storage layer disposed over the tunnel barrier layer, and a capping layer disposed over the magnetic storage layer. Further, the film stack comprises at least one protection layer disposed between the magnetic reference layer and the tunnel barrier layer and disposed between the magnetic storage layer and the capping layer. Additionally, a material forming the at least one protection layer differs from at least one of a material forming the magnetic reference layer and a material forming the magnetic storage layer.

Magnetic tunnel junctions with protection layers

Growing community of inventors

Fremont, CA, United States of America

Sahil Patel