Cadence Design Systems, Inc.

Nxp Usa, Inc.

Sahil Jain

Akhil Garg

Vivek Chickermane

Dale Meehl

A system-on-chip (SoC) is disclosed. The SoC includes a set of input channels, a first partition including a set of output wrapper chains, a set of output channels, a second partition including a set of input wrapper chains, and an inter-partition circuit coupled between the first and second partitions. During an external test mode, the set of input channels receives input test data. The set of output wrapper chains receives and stores intermediate data that is generated based on the input test data. The inter-partition circuit receives the intermediate data from the set of output wrapper chains and generates test response data based on the intermediate data. The set of input wrapper chains receives the test response data, and provides the test response data to be captured as output test data at the set of output channels to test the inter-partition circuit.

Scan wrapper architecture for system-on-chip

A test circuit includes a plurality of codec logic elements arranged in a plurality of annular rings on an integrated circuit, each codec logic element configured to provide test bits to one or more respective scan chain and receive test result bits from the one or more respective scan chain. The test circuit further includes a decompressor logic arranged along at least one annular ring of the plurality of annular rings on the integrated circuit, the decompressor logic configured to provide test bits to at least one codec logic element in each annular ring. The test circuit also includes a compressor logic arranged transversely with respect to the plurality of annular rings on the integrated circuit, the compressor logic configured to receive test result bits from at least one of the plurality of codec logic elements.

Test circuitry with annularly arranged compressor and decompressor elements

Embodiments relate to providing security of scan mode access and data in an integrated circuit. In embodiments, one or both of two layers of security are provided. A first layer includes requiring a complex initialization sequence to be performed in order to access scan mode. A second layer includes scrambling the scan data before it is output from the circuit under test, which prevents unauthorized persons from extracting useful information from the output scan data. Further embodiments relate to methodologies for utilizing these protection layers after manufacture of the integrated circuit and incorporating these protection layers in an integrated circuit design flow.

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Ghaziabad, India

Sahil Jain