Advanced Micro Devices Corporation

Sahil Arora

Srikanth Arekapudi

Emil Talpes

Marius Evers

Debjit Das Sarma

Nikhil Gupta

Wei-Yu Chen

Douglas R Williams

A processor, a device, and a non-transitory computer readable medium for performing branch prediction in a processor are presented. The processor includes a front end unit. The front end unit includes a level 1 branch target buffer (BTB), a BTB index predictor (BIP), and a level 1 hash perceptron (HP). The BTB is configured to predict a target address. The BIP is configured to generate a prediction based on a program counter and a global history, wherein the prediction includes a speculative partial target address, a global history value, a global history shift value, and a way prediction. The HP is configured to predict whether a branch instruction is taken or not taken.

Bandwidth increase in branch prediction unit and level 1 instruction cache

A processor includes an execution unit to execute instructions and a scheduler unit to store a queue of instructions for execution by the execution unit. The scheduler unit includes a wake array including a plurality of source slots to store source identifiers for sources associated with the instructions, a picker to schedule a particular instruction for execution in the execution unit, broadcast a destination identifier associated with the particular instruction to a first subset of the source slots, and a delay element to receive the destination identifier broadcast by the picker and communicate a delayed version of the destination identifier to a second subset of the source slots different from the first subset.

Tracking source availability for instructions in a scheduler instruction queue

Growing community of inventors

Campbell, CA, United States of America

Sahil Arora