Samsung Electronics Co., Ltd.

University of California

Sahand Salamat

Yang Seok Ki

Hui Zhang

Joo Hwan Lee

Zongwang Li

Rekha Pitchumani

Praveen Krishnamoorthy

Mohsen Imani

Armin Haj Aboutalebi

Tajana Rosing

Xiaodong Zhao

Behnam Khaleghi

A method of defining an implementation of circuits in a programmable device can be provided by receiving a plurality of specifications for a hyperdimensional (HD) computing machine learning application for execution on a programmable device, determining parameters for a template architecture for HD computing machine learning using the plurality of specifications, the template architecture including an HD hypervector encoder, an HD associative search unit, programmable device pre-defined processing units, and programmable device pre-defined processing elements within the pre-defined processing units, and generating programmable device code configured to specify resources to be allocated within the programmable device using pre-defined circuits defined for use in the programmable device using the determined parameters for the template architecture.

Methods and systems configured to specify resources for hyperdimensional computing implemented in programmable devices using a parameterized template for hyperdimensional computing

Provided is a method of data storage, the method including receiving, from an application, a request to access data stored on a storage device, identifying a data access pattern of the application, and storing the data in a cache of the storage device based on the data access pattern.

Adaptive cache indexing for a storage device

An accelerator is disclosed. The accelerator may include a memory that may store a dictionary table. An address generator may be configured to generate an address in the dictionary table based on an encoded value, which may have an encoded width. An output filter may be configured to filter a decoded value from the dictionary table based on the encoded value, the encoded width, and a decoded width of the decoded data. The accelerator may be configured to support at least two different encoded widths.

Near-storage acceleration of dictionary decoding

A storage system includes: a storage device to store an array of data elements associated with a sort operation; a storage interface to facilitate communications between the storage device and a host computer; and a reconfigurable processing device communicably connected to the storage device, the reconfigurable processing device including: memory to store input data read from the storage device, the input data corresponding to the array of data elements stored in the storage device; and a kernel including one or more compute components to execute the sort operation on the input data stored in the memory according to a SORT command received from the host computer. The reconfigurable processing device is to dynamically instantiate the one or more compute components to accelerate the sort operation.

System and method for hierarchical sort acceleration near storage

Growing community of inventors

San Bruno, CA, United States of America

Sahand Salamat