Stmicroelectronics International N.v.

Adobe, Inc.

Sagnik Mukherjee

Ankit Gupta

Nitin Kumar Gupta

Niyati Himanshu Chhaya

Fan Du

Aparna Garimella

Saurabh Mahapatra

Sharmila Reddy Nangi

Sapthotharan Krishnan Nair

Snehal Raj

Jay Mundra

Atharv Tyagi

A text summarization system auto-generates text summarization models using a combination of neural architecture search and knowledge distillation. Given an input dataset for generating/training a text summarization model, neural architecture search is used to sample a search space to select a network architecture for the text summarization model. Knowledge distillation includes fine-tuning a language model for a given text summarization task using the input dataset, and using the fine-tuned language model as a teacher model to inform the selection of the network architecture and the training of the text summarization model. Once a text summarization model has been generated, the text summarization model can be used to generate summaries for given text.

Auto-creation of custom models for text summarization

A PLL circuit includes a fractional-N divider generating a feedback signal, a first phase-frequency detector that compares the feedback signal to a reference signal to generate first up/down control signals that control a charge pump to generate a charge pump output current. A noise cancelation circuit includes a synchronization circuit that generates first and second synchronized feedback signals from the PLL circuit output and the feedback signal, where the first and second synchronized feedback signals are offset by an integer number of cycles of the PLL circuit output. A second phase-frequency detector circuit compares the first and second synchronized feedback clock signals to generate second up/down control signals whose pulse widths differ by the integer number of PLL cycles. A current digital to analog converter circuit is controlled in response to the second up/down control signals to apply noise canceling sourcing and sinking currents to the charge pump output current.

Fractional-N phase lock loop (PLL) with noise cancelation

A PLL includes a phase-frequency-detector-and-charge-pump-circuit (PFDCPC) receiving a reference signal and divided signal, and generating a charge-pump current. A loop-filter is between output of the PFDCPC and a reference-voltage. A first voltage-to-current converter (V2I1) has low gain, and a second voltage-to-current converter (V2I2) has high gain. A low-gain-path is between outputs of the PFDCPC and V2I1, and a high-gain-path is between the outputs of the PFDCPC and V2I2. A current-controlled-oscillator receives an input signal, and generates an output signal. A loop divider divides the output signal by a divider-value, producing the divided signal. The low-gain-path runs directly from the PFDCPC, through the V2I1, to the input of the current-controlled-oscillator. The high-gain-path runs from the PFDCPC to the loop-filter, from a tap of the loop-filter to a low-pass filter through a current mirror, from a tap of the low-pass filter through the V2I2, to the input of the current-controlled-oscillator.

Charge pump phase locked loop with low controlled oscillator gain

A voltage controlled oscillator (VCO) circuit generates an output signal having a frequency which is dependent on a control voltage. A current is generated which is itself dependent on an amplitude of the VCO circuit. The generated current accordingly tracks, to an extent, the temperature behavior of the oscillator within the VCO circuit. The oscillator is driven by the sum of the generated current and a control current dependent on the control voltage. The control voltage may, for example, be generated by a phase lock loop (PLL).

Phase locked loop (PLL) circuit with voltage controlled oscillator (VCO) having reduced gain

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Kolkata, India

Sagnik Mukherjee