Sunrise Memory Corporation

Sagie Goldenberg

Shay Fux

Amotz Yagev

Shahar Sandor

A memory device includes: (a) one or more memory circuits having physical memory pages identified by physical page addresses, each physical memory page being provided to store a memory page; and (b) a control circuit configured for managing read or write operations in each memory circuit. The control circuit manages both a wear-leveling scheme and read and write operations in the memory circuits.

Wear-level control circuit for memory module

A memory system includes a memory device including an array of storage transistors organized in multiple memory banks, each memory bank including multiple memory pages; and a control circuit configured to interact with the memory device to perform read and write operations. The control circuit includes a read queue configured to store active read requests for reading data from the memory device, a write queue configured to store active write requests for writing data to the memory device, a command selector to select one or more commands issued by the read queue or the write queue, and a virtual to physical address translator to convert the memory address of the selected command encoded with the virtual bank index to a corresponding memory physical addresses, the selected command with the memory physical address being issued to the memory device for execution at the memory device.

Memory controller for a high capacity memory circuit using virtual bank addressing

A memory system includes a memory device including an array of storage transistors for storing data where the storage transistors are organized in multiple memory banks, each memory bank including multiple memory pages; and a control circuit configured to interact with the memory device to perform read and write operations. The control circuit includes a read queue configured to store active read requests for reading data from the memory device, a write queue configured to store active write requests for writing data to the memory device, and a write staging buffer configured to store pending write requests received by the control circuit and to transfer the pending write requests to the write queue to maximize the number of active write requests that are addressed to different memory banks of the memory device.

Memory controller including a write staging buffer to manage write requests for a high capacity memory circuit with large number of independently accessible memory banks

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Gaaton, Israel

Sagie Goldenberg