Intel Corporation

Sagi Lahav

Zeev Sperber

Ittai Anati

Shih-Lien L Lu

Herbert H Hum

Srikanth T Srinivasan

Guillermo Savransky

Guy Patkin

Yuval Bustan

Asi Joseph

Ofer Sierra

A device and method may fetch an instruction or micro-operation for execution. An indication may be made as to whether the instruction is dependent upon any source values corresponding to a set of previously fetched instructions. A value may be stored corresponding to each source value from which the first instruction depends. An indication may be made for each of the set of sources of the instruction, whether the source depends on a previously loaded value or source, where indicating may include storing a value corresponding to the indication. The instruction may be executed after the stored values associated with the instruction indicate the dependencies are satisfied.

System and method for reservation station load dependency matrix

A partial execution unit of a splittable execution unit performs an operation on a portion of one or more arguments of a micro-operation to generate a first partial execution result of the micro-operation. A complementary portion of one of the arguments is passed through a bypass execution unit instead of through the splittable execution unit to generate a second partial execution result of the micro-operation. The first partial execution result and second partial execution result are concatenated into a full execution result.

Apparatus and methods for utilization of splittable execution units of a processor

Periods of futile activity by one or more logic circuits of a component of a processor may be predicted, and then during each such period, one or more of the logic circuits may operate in a power-save state with reduced power consumption, with the latter part of the period being used to bring the logic circuits back into performance state, so that performance is not diminished beyond an acceptable level due to the power-save state. The decision of whether to reduce the power consumption of a particular logic circuit of a particular processor component is to have at a particular future time is made internally in the particular processor component based on one or more signals received by the particular processor component.

Processor and methods to reduce power consumption of processor components

In some embodiments of the present invention, one or more elements of a processor core may receive a signal indicating that operands of a micro-instruction are narrow, for example less than or equal to 32 bits. In response to this signal, one or more components of a processor core element that are able to handle more than 32 bits of data (e.g. operands or results) may function as though they handle only 32 bits of data.

Processor core and methods to reduce power by not using components dedicated to wide operands when a micro-instruction has narrow operands

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Kiryat Motzkin, Israel

Sagi Lahav