Apple Inc.

Mellanox Technologies, Ltd.

Sagi Lahav

Lior Zimet

Lital Levy-Rubin

Harshavardhan Kaushikkar

Gaurav Garg

Per Hakan Hammarlund

Sergio Kolor

James Vash

Shawn Munetoshi Fukami

Gerard Richard Williams

Srinivasa Rangan Sridharan

Jonathan M Redshaw

Steven R Hutsell

Tzach Zemer

Eran Tamari

Samer Nassar

Sergio V Tota

Gil Levy

Steven John Fishwick

Shie Mannor

Jeff Gonion

Charles J Fleckenstein

Amir Rosen

Arye Albahari

Igor Tolchinsky

Jeffry E Gonion

Doron Rajwan

Tal Kuzi

Charles E Tucker

Dany Davidov

Nir Leshem

Mark Pilip

Ariel Szapiro

Roey Grinvald

Elad Alon

Dan Darel

Roi Uziel

In one embodiment, a system includes prefetcher engines to predict next memory access addresses of a memory from which to load data to a cache during execution of a software application, and load the data from the predicted next memory access addresses to the cache during execution of the software application, and a processor to control the prefetcher engines according to configurations of the prefetcher engines selected by a machine learning agent in exploration phases and in exploitation phases during execution of the software application, and execute the machine learning agent to select from a pruned set of configurations to control the prefetcher engines in the exploration phases, perform measurements on the system during execution of the machine learning agent, and execute the machine learning agent to select from the configurations to maximize potential rewards from controlling the prefetcher engines in the exploitation phases based on the performed measurements.

Prefetcher engine configuration selection with multi-armed bandit

In one embodiment, a system includes prefetcher engines to predict next memory access addresses of a memory from which to load data to a cache during execution of a software application, and load the data from the predicted next memory access addresses to the cache during execution of the software application, and a processor to assign cache replacement precedence values to cache lines based on the prefetcher engines that loaded the cache lines, and evict the cache lines from the cache based on the cache replacement precedence values of the cache lines.

Cache replacement system

In one embodiment, a system includes a processor to reduce a number of cache replacement precedence value policies available for selection by a machine learning agent, each cache replacement precedence value policy including an array of predefined cache replacement precedence values for corresponding different combinations of (a) prefetcher engines that loaded cache lines, and (b) event-types of events that have been performed on the cache lines, and a memory to store data used by the processor.

Reducing set of policies with two or more hyper-dimensions

An apparatus includes first agents configured to transfer transactions using an ordered protocol, as well as second agents configured to transfer transactions using a protocol with no enforced ordering. The apparatus may also include input/output (I/O) interfaces coupled to respective ones of the first agents and configured to enforce the ordered protocol. The apparatus may further include a communication network including a plurality of network switches. A particular one of the network switches may be coupled to at least one other network switch of the plurality. The apparatus may also include a network interface coupled to the second agents, to the I/O interfaces, and to the particular network switch. This network interface may be configured to transfer data transactions between the second agents and the particular network switch, and to transfer data transactions between the I/O interfaces and the particular network switch.

Communication fabric structures for increased bandwidth

A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

Scalable system on a chip

A system for a given device may include a plurality of systems on a chip (SOCs). Each SOC may include an interface circuit and a bridge circuit for communicating with other SOCs. The interface circuit of an SOC may include a plurality of communication devices to transfer data packets from/to the SOC to the other SOCs. The bridge circuit may provide various control functions for the interface circuit. An indication may be generated when the system enters an idle mode. In response, the bridge circuit may generate signal(s) to cause some of the communication devices of the interface circuit into a low power state. The interface circuit may obtain the signal(s) and accordingly transition some of the communication devices to the low power state.

Dynamic interface circuit to reduce power consumption

In an embodiment, an SOC includes a global communication fabric that includes multiple independent networks having different communication and coherency protocols, and a plurality of input-output (I/O) clusters that includes different sets of local functional circuits. A given I/O cluster may be coupled to one or more of the independent networks and may include a particular set of local functional circuits, a local fabric coupled to the particular set of local functional circuits, and an interface circuit coupled to the local fabric and configured to bridge transactions between the particular set of local functional circuits and the global communication fabric. The interface circuit may include a programmable hardware transaction generator circuit configured to generate a set of test transactions that simulate interactions between the particular set of local functional circuits and a particular one of the one or more independent networks.

Transaction generator for on-chip interconnect fabric

Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include a memory bank and be coupled to a set of devices. The I/O agent circuit may assign a device of the set of devices to a subdomain of a plurality of subdomains implemented for the memory bank. The I/O agent circuit may store, in that memory bank, a set of transactions of the device in association with the subdomain assigned to the device. The I/O agent circuit may execute the set of transactions such that transactions stored in the memory bank in association with other ones of the plurality of subdomains than the subdomain assigned to the device do not block execution of the set of transactions.

Memory bank with subdomains

Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include one or more queues and a transaction pipeline. The I/O agent circuit may issue, to the transaction pipeline from a queue of the one or more queues, a transaction of a series of transactions enqueued in a particular order. The I/O agent circuit may generate, at the transaction pipeline, a determination to return the transaction to the queue based on a detection of one or more conditions being satisfied. Based on the determination, the I/O agent circuit may reject, at the transaction pipeline, up to a threshold number of transactions that issued from the queue after the transaction issued. The I/O agent circuit may insert the transaction at a head of the queue such that the transaction is enqueued at the queue sequentially first for the series of transactions according to the particular order.

Ensuring transactional ordering in I/O agent

An electronic device includes circuitry and a plurality of ports. The plurality of ports includes an input port and an output port, configured to communicate data units with one or more other devices across a fabric of a System on a Chip (SoC), the data units include N data bits, N being an integer larger than 1. The circuitry is configured to receive an input data unit via the input port, to make a random decision of whether to invert the N data bits in the input data unit, to produce an output data unit by retaining or inverting the N data bits of the input data unit based on the random decision, and to send the output data unit via the output port.

Power consumption control based on random bus inversion

An integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. For example, the IC may include an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices; and an off-chip interconnect coupled to the interconnect fabric and configured to couple the interconnect fabric to a corresponding interconnect fabric on another instance of the integrated circuit, wherein the interconnect fabric and the off-chip interconnect provide an interface that transparently connects the one or more memory controller circuits, the processor cores, graphics processing units, and peripheral devices in either a single instance of the integrated circuit or two or more instances of the integrated circuit.

In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.

Multiple independent on-chip interconnect

Techniques are disclosed relating to an I/O agent circuit of a computer system. The I/O agent circuit may receive, from a peripheral component, a set of transaction requests to perform a set of read transactions that are directed to one or more of a plurality of cache lines. The I/O agent circuit may issue, to a first memory controller circuit configured to manage access to a first one of the plurality of cache lines, a request for exclusive read ownership of the first cache line such that data of the first cache line is not cached outside of the memory and the I/O agent circuit in a valid state. The I/O agent circuit may receive exclusive read ownership of the first cache line, including receiving the data of the first cache line. The I/O agent circuit may then perform the set of read transactions with respect to the data.

Growing community of inventors

Kiryat Bialik, Israel

Sagi Lahav