Freescale Semiconductor,inc.

Sagi Gurfinkel

Uri Shasha

Gilad Hassid

Eran Kahn

Yehuda Shvager

A method for arbitrating between direct memory access task requests, the method includes receiving multiple DMA task requests; the method is characterized by selecting a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks. A device that includes an interface, that is adapted to receive DMA task requests; the device is characterized by including an arbiter that is adapted to select a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks.

Device and method for arbitrating between direct memory access task requests

A method for controlling an execution of a first DMA task, the method includes comprises monitoring an execution of the first DMA task, the method characterized by including defining a first DMA task execution interval and a first DMA task execution sub-interval; and performing a first possible timing violation responsive operation if the first DMA task was not completed during the first DMA task execution sub-interval. A device having a first DMA task controlling capabilities, the device includes a memory unit; characterized by including a DMA controller that is adapted to monitor an execution of the first DMA task that involves an access to the memory unit, and to perform a first possible timing violation responsive operation if the first DMA task was not completed during a first DMA task execution sub-interval.

Device and method for controlling an execution of a DMA task

A method for controlling multiple DMA tasks, the method includes receiving multiple DMA task requests; the method is characterized by defining multiple buffer descriptors for each of a plurality of DMA channel; wherein at least two buffer descriptors comprise timing information that controls an execution of cyclic time based DMA tasks; selecting a DMA task request out of the multiple DMA task requests; executing a DMA task or a DMA task iteration and updating the buffer descriptor associated with the selected DMA task request to reflect the execution; and jumping to the stage of selecting. A device that includes a memory unit; the device is characterized by including a DMA controller that is adapted to: (i) access at least one buffer descriptor out of multiple buffer descriptors defined for each of a plurality of DMA channel, wherein at least two buffer descriptors comprise timing information that controls an execution of cyclic time based DMA tasks; (ii) receive multiple DMA task requests, (iii) select a DMA task request out of the multiple DMA task requests, and (iv) execute a DMA task or a DMA task iteration and update a buffer descriptor associated with the selected DMA task request to reflect the execution.

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Austin, TX, United States of America

Sagi Gurfinkel