Intel Corporation

Sagar Suthram

Tahir Ghani

Anand S Murthy

Wilfred Gomes

Abhishek A Sharma

Rishabh Mehandru

Sairam Subramanian

Gokul Malyavanatham

Abhishek Anil Sharma

Manish Sharma

Seung-June Choi

Vishal Javvaji

Amit Paliwal

Ahmed Esmail

Soumya Kar

David Sanchez

Enlan Yuan

IC devices including angled transistors formed based on angled wafers are disclosed. An example IC device includes a substrate and a semiconductor structure. A crystal direction of a crystal structure in the semiconductor structure is not aligned with a corresponding crystal direction (e.g., having same Miller indices) of a crystal structure in the substrate. An angle between the two crystal directions may be 4-60 degrees. The semiconductor structure is formed based on another substrate (e.g., a wafer) that has a different orientation from the substrate, e.g., flats or notches of the two substrates are not aligned. The crystal direction of the semiconductor structure may be determined based on a crystal direction in the another substrate. The semiconductor structure may be a portion of a transistor, e.g., the channel region and S/D regions of the transistor. The semiconductor structure may be angled with respect to an edge of the substrate.

Integrated circuit devices with angled transistors formed based on angled wafers

Structures having ultra-high conductivity global routing are described. In an example, an integrated circuit structure includes a device layer having a plurality of transistors. A plurality of metallization layers is above the plurality of transistors of the device layer. One or more of the metal layers includes a material having a critical temperature greater than 10 Kelvin and less than 300 Kelvin.

Integrated circuit structures having ultra-high conductivity global routing

A semiconductor structure is disclosed. The semiconductor structure includes back end layers that include a first metallization layer, a second metallization layer, and a scalable resistor between the first metallization layer and the second metallization layer. The semiconductor structure also includes front end layers.

And process for a precision resistor

Embodiments of the present disclosure relate to in-line detection of electrical fails on integrated circuits. One embodiment is an apparatus including a device region with integrated circuits and a test region for in-line failure detection of the integrated circuits using an in-line voltage contrast test, the apparatus comprising: a substrate including a first area for the device region and a second different area for the test region; metal layers formed over both areas; wherein the integrated circuits are formed from first sections of the layers; and wherein a second section of an upper metal layer of the layers is segmented into test segments, each test segment to exhibit a predefined response during the in-line voltage contrast test depending on whether the test segment is shorted, or not, to the substrate and/or the second section of a gate layer of the layer. Other embodiments may be disclosed and/or claimed.

In-line detection of electrical fails on integrated circuits

Growing community of inventors

Portland, OR, United States of America

Sagar Suthram