Apple Inc.

Nvidia Corporation

Sagar Nataraj

Bo Yang

Derek Keith Shaeffer

Amit D Sanghani

Henry C Jen

Xiang Lu

Karthikeyan Natarajan

Karthik Manickam

Andrew J Copperhall

Shriram Vijayakumar

Design-for-test (DFT) architectures, and methods of testing an array of chips, which may be identical, are described. In an embodiment, a comparison circuit includes a plurality of comparators to compare scan-data out (SDO) data streams with an expected data stream and transmit a compared data stream that is indicated of whether or not an error exists in any of the SDO data streams.

Test-response comparison circuit and scan data transfer scheme in a DFT architecture for micro LED based display panels

Various aspects described or referenced herein are directed to different methods, systems, and computer program products for implementing hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support.

Hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support

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San Jose, CA, United States of America

Sagar Nataraj