Altera Corporation

Synopsys, Inc.

Insilicon Corporation

Sagar Edara

Mammen Thomas

Neil Mammen

Greg Maturi

Ramana Kalapatapu

Amjad Qureshi

Ajit Deora

An apparatus is described having a plurality of network processors that identify, for each of a plurality of packets, which multidimensional queue from amongst a plurality of multidimensional queues that each one of the plurality of packets should be enqueued into. Each of the network processors is able to identify a particular multidimensional queue for a different one of the plurality of packets.

Method and apparatus for using multiple network processors to achieve higher performance networking applications

According to one embodiment, a network is disclosed. The network includes a source device, a networking hardware machine coupled to the source device, and a destination device coupled to the networking hardware machine. The networking hardware machine receives data packets from the source device and distributes statistics data corresponding to the data packets among multiple internal memory devices.

Mechanism for distributing statistics across multiple elements

A system on-chip interface device includes a plurality of cores comprising core systems a plurality of standard interfaces interfaced to the plurality of cores a system bus, an on-chip bus, a plurality of system interface blocks comprising first and second interfaces, wherein the first interface comprises a standard interface interfaced to at least one core system and the second interface comprises an interface interfaced to the system bus, a system bus bridge comprising first and second system bus interfaces wherein the first system bus interface comprises an interface interfaced to the system bus and the second system bus interface comprises a standard interface, an on-chip bus bridge comprising first and second on-chip bus interfaces wherein the first on-chip bus interface comprises a standard interface interfaced to the system bus bridge and the second on-chip bus interface comprises an interface interfaced to the on-chip bus.

Method and apparatus for providing a modular system on-chip interface

Two on-chip buses (OCBs) having respective standardized definitions are implemented on a multi-function system chip, with one of the OCB definitions being a subset of the other. System virtual components (VCs) are connected to the system OCB with a system virtual component interface or &ldquo;bus wrapper&rdquo;. &ldquo;Peripheral&rdquo; virtual components are connected to a peripheral OCB using respective standard interface blocks. Since the definition of the peripheral OCB is a subset of the system OCB, bridging between the two OCBs is relatively straightforward. The invention permits a &ldquo;plug and play' capability on behalf of all peripheral VC designs implemented according to the standard, such that the systems integrator may mix and match peripheral VCs without degradation of functionality or performance.

Growing community of inventors

San Jose, CA, United States of America

Sagar Edara