Advanced Micro Devices Corporation

Saf M Asghar

Mark A Ireton

John G Bartkowiak

Brett B Stewart

Yan Zhou

Russell W Bell

Andrew Mills

Sherman E Lee

David Francis Tobias

Michael E Spak

Paul R Teich

Philip Chu Yip

Muhammad M Rahmatullah

Hwa-Sheng Pyi

Described herein is a network interface for coupling residential appliances into a code-division multiple access (CDMA) network. The network is used to convey appliance control signals and appliance status signals. The network interface includes a transmitter and/or a receiver, depending on the communications needs of the residential appliance. A spreading-code generator in the network interface generates a spreading code that identifies the residential appliance. A spreading mixer modulates a narrowband transmit signal with the spreading code, thereby generating a spread-spectrum transmit signal. The wideband transmit signal is then coupled into the physical medium of the network. In one embodiment, the physical medium is a residential wiring grid, and a wiring interface in the transmitter unit couples the spreading mixer with the residential wiring. Spread-spectrum signals received from the wiring grid are despread with an appropriate spreading code to extract the desired signal. Also described herein is a network interface for a wired network. The network interface includes a modulator configured to receive a stream of transmit data and to generate a modulated carrier signal from the data. The modulated carrier is spread by a direct-sequence spreading circuit, using a node-specific spreading code, into a wideband signal. The wideband signal is then coupled onto the wired network.

Home-appliance network with nodes identified by direct-sequence spreading codes

A computing device, such as a laptop personal computer (PC), a desktop PC, or a personal information device (PID), includes an antenna embedded therein for wireless communications. The antenna may be formed on a printed circuit board installed in the computing device. The antenna may include multiple radiating and receiving elements for mitigating multipath effects and/or responding to steering circuitry to form a directed antenna beam.

PC wireless communications utilizing an embedded antenna comprising a

A digital communication system includes a receiver and a transmitter in communication with the receiver over a communication link. The transmitter includes a buffer circuit which receives input data signals for transmission and a control signal. The buffer circuit outputs buffered data signals. A symbol encoder circuit receives the buffered data signals and provides the control signal. The symbol encoder circuit outputs data symbols over the communication link. The buffered data signals are supplied to the symbol encoder circuit in accordance with the control signal. The data symbols may be encoded with a number of data bits. The encoding may be done by voltage-level encoding.

Method of and apparatus for encoding of output symbol size

A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. In a first embodiment, the CPU receives general purpose instructions, such as X86 instructions, wherein certain X86 instruction sequences implement DSP functions. The CPU includes a processor mode register which is written with one or more processor mode bits to indicate whether an instruction sequence implements a DSP function. The CPU also includes an intelligent DSP function decoder or preprocessor which examines the processor mode bits and determines if a DSP function is being executed. If a DSP function is being implemented by an instruction sequence, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. If the processor mode bits indicate that X86 instructions in the instruction memory do not implement a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems. In a second embodiment, the CPU receives sequences of instructions comprising X86 instructions and DSP instructions. The processor mode register is written with one or more processor mode bits to indicate whether an instruction sequence comprises X86 or DSP instructions, and the instructions are routed to the X86 core or to the DSP core accordingly.

Central processing unit including APX and DSP cores and including

Central processing unit including APX and DSP cores which receives and

The present invention comprises a system and method for a GSM receiver to perform channel estimation under the assumption that the analog-to-digital (A/D) converter is free-running. A search process is employed, whereby the known GSM training signal is sampled with a plurality of phases which vary incrementally from zero to a full symbol period. For each phase a sample set (of the training signal) is generated. Furthermore, each sample set is used, together with the received samples, in a cross-correlation procedure to obtain a candidate impulse response vector for the transmission channel. Thus a plurality of candidate impulse response vectors are produced, one of which will be selected to be the optimal representative for the transmission channel. The optimal impulse response vector is selected as follows. Each impulse response vector is convolved with the corresponding sample set, thus producing an estimated output vector. The estimated output vectors are compared with the vector of received samples (from the free-running A/D converter), and the estimated output vector which is closest in the Euclidean (square-norm) sense designates the impulse response vector which is optimal.

System and method for estimating a set of parameters for a transmission

A method of processing incoming ethernet frames includes the steps of storing a header of each incoming ethernet frame in a header column of a buffer array, storing a data field of each incoming ethernet frame in a data column of the buffer array, each data field being stored in a same row of the buffer array as a corresponding header, and storing a CRC of each incoming ethernet frame in a CRC column which is next to the header column, each CRC being stored in a same row of the buffer array as a corresponding header and a corresponding data field. The method can further include the step of evaluating each stored CRC based on the header stored next to the CRC. In one alternative, the header column is between the CRC column and the data column. In another alternative, the CRC column is between the header column and the data column. Also provided is a virtual circular buffer which includes an input frame segmentation unit, a header column connected to the frame segmentation unit, a data field column next to the header column, the data field column being connected to the frame segmentation unit, and a CRC column next to the header column, the CRC column being connected to the frame segmentation unit, wherein the frame segmentation unit receives incoming frames and stores a header of each incoming frame into the header column, a data field of each incoming frame into the data field column next to a corresponding header, and a CRC of each incoming frame into the CRC column next to the corresponding header.

Communication processing method using a buffer array as a virtually

A modulated bus interconnects each of the plurality of elements on the bus through a filter having a center frequency corresponding to a carrier frequency which modulated by digital information destined for the particular device. Since the device receives an incoming message through a filter, it detects only those messages which have the appropriate filter characteristics. In order to send a message to another device, the first device must apply the appropriate carrier. Thus, multiple transfers between multiple devices can take place simultaneously on a wide-band transmission medium. A controller can be used to dynamically allocate the bus according to an efficient allocation scheme.

Modulated bus computer system having filters with different frequency

A method of communicating a video image via an audio communication signal includes the steps of identifying, for a given pixel location of the video image, a set of samples within a stored audio signal having a corresponding bit pattern, generating a marker identifying the location of the given pixel in the video image, and multiplexing the stored audio signal and the marker such that the marker appears within the stored audio signal proximate to the set of samples having the corresponding bit pattern. This method can also include the steps of transmitting the multiplexed signal to a destination device, demultiplexing, at the destination device, to recover the marker and the corresponding bit pattern, illuminating a display at the given pixel location according to the corresponding bit pattern, and converting the corresponding bit pattern into an analog audio signal.

Method of using an audio transmission signal to transmit video data

A digital voice data storage and retrieval system using a low bit rate encoder which provides enhanced speech signal quality while also reducing memory size requirements. The system comprises a voice coder/decoder which preferably includes a digital signal processor (DSP) and also preferably includes a local memory. During encoding of the voice data, the voice coder/decoder receives voice input waveforms and generates a parametric representation of the voice data. A storage memory is coupled to the voice coder/decoder for storing the parametric data. During decoding of the voice data, the voice coder/decoder receives the parametric data from the storage memory and reproduces the voice waveforms. According to the invention, an interframe smoothing method is performed on the parametric data after encoding of all of the speech data has completed and the parametric data has been stored in the storage memory. The interframe smoothing is performed either in the background after the coding process has completed or in real time during the decoding process immediately prior to converting the parametric data back to signal waveforms. Since all of the voice input data has already been converted to parametric data and stored in memory, parametric data from a virtually unlimited number of prior and successive frames is available for use by the smoothing algorithm. Therefore, the present invention provides more accurate smoothing and provides enhanced speech signal quality over prior systems.

System and method for enhanced speech quality in voice storage and

A method of executing a program includes reading a next operation of an executing program and determining if a given pointer corresponding to the next operation is stored in a pointer table. If the given pointer is stored in the pointer table, an instruction identified by the given pointer is executed in a processor. However, if the given pointer is not stored in the pointer table, a replaceable pointer in the pointer table is identified and replaced by the given pointer. Instructions corresponding to the given pointer are also imported into a processor instruction unit from a supplemental storage area and subsequently executed by the processor. The instructions can comprise microcode or a portion of a programmable gate array. In the latter case, the supplemental storage area can store gate array programming instructions for use in reprogramming the instructions in the processor. When replacing a pointer in the pointer table, a least recently used algorithm or a most recently used algorithm are provided as examples of methods for defining the replaceable pointer. A retargetable VLIW computer architecture for carrying out this method includes a program execution unit, a pointer table, a processor, a processor instruction unit, and a supplemental storage area. The architecture further includes interconnections between the aforementioned elements for updating the pointer table to replace a replaceable pointer with a given pointer and for replacing one or more instructions corresponding to the replaceable pointer with one or more instructions corresponding to the given pointer.

Retargetable VLIW computer architecture and method of executing a

A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X86 opcode sequences and determines if a DSP function is being executed. If the DSP function decoder determines that a DSP function is being executed, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. The DSP core implements or performs the DSP function using a lesser number of instructions and also in reduced number of clock cycles, thus increasing system performance. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems. The X86 core and the DSP core are coupled to each other and communicate data and timing signals for synchronization purposes. Thus, the DSP core offloads these mathematical functions from the X86 core, thereby increasing system performance. The DSP core also operates in parallel with the X86 core, providing further performance benefits. The CPU of the present invention thus implements DSP functions more efficiently than X86 logic while requiring no additional X86 opcodes. The present invention also generates code that operates transparently on an X86 only CPU or a CPU according to the present invention which includes X86 and DSP cores. Thus the present invention is backwards compatible with existing software.

CPU with DSP having function preprocessor that converts instruction

A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, an also includes a DSP core. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X86 opcode sequences and determines if a DSP function is being executed. If the DSP function decoder determines that a DSP function is being executed, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. The DSP core implements or performs the DSP function using a lesser number of instructions and also in reduced number of clock cycles, thus increasing system performance. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems. The X86 core and the DSP core are coupled to each other and communicate data and timing signals for synchronization purposes. Thus, the DSP core offloads these mathematical functions from the X86 core, thereby increasing system performance. The DSP core also operates in parallel with the X86 core, providing further performance benefits. The CPU of the present invention thus implements DSP functions more efficiently than X86 logic while requiring no additional X86 opcodes. The present invention also generates code that operates transparently on an X86 only CPU or a CPU according to the present invention which includes X86 and DSP cores. Thus the present invention is backwards compatible with existing software.

Central processing unit including a DSP function preprocessor which

A configurable multiprocessor communications architecture which performs digital communications functions and which is configurable for different digital communications standards, such as various digital cellular standards. In the preferred embodiment, the multiprocessor architecture includes two or more digital signal processing cores, a microcontroller or micro-scheduler, a voice coder/decoder (codec), and a relatively low performance central processing unit (CPU). Each of the above devices are coupled to a system memory. The general purpose CPU preferably performs user interface functions and overall communications management functions. A CPU local memory and various peripheral devices are coupled through a CPU local bus to the CPU, and these devices are accessible to the CPU without the CPU having to access the main system bus. A dual port bus arbiter is preferably coupled between the CPU and the system bus and controls access to the system bus and the CPU local bus. The micro-scheduler operates to schedule operations and/or functions, as well as dynamically control the clock rates, of each of the DSPs and the hardware acceleration logic to achieve the desired throughput while minimizing power consumption. The present invention thus provides a single architecture which has simplified configurability for different digital standards. The configurable digital communications architecture simplifies design and manufacturing costs and provides improved performance over prior designs.

Configurable digital wireless and wired communications system

A CPU or microprocessor which includes a general purpose CPU, such as an X86 core, and a DSP. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X8 opcode sequences and determines if a DSP function is being executed. The function preprocessor includes a look-up table which stores instruction sequences which implement DSP functions. Each pattern in the look-up table is compared with an instruction sequence to determine if one of the patterns substantially matches the instruction sequence. If the DSP function preprocessor determines that a DSP function is being executed, the DSP function preprocessor converts the opcodes to a DSP macro instruction that is provided to the DSP. The DSP executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core. Thus, the DSP offloads these mathematical functions from the X86 core, thereby increasing system performance. The DSP operates in parallel with the X86 core, providing further performance benefits. The CPU of the present invention thus implements DSP functions more efficiently than X86 logic while requiring no additional X86 opcodes. The present invention also generates code that operates transparently on an X86 only CPU or a CPU according to the present invention which includes X86 and DSPs. Thus the present invention is backwards compatible with existing software.

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Austin, TX, United States of America

Saf M Asghar