Skhynix Inc.

Hynix Semiconductor Inc.

Saeng Hwan Kim

Mun Seon Jang

Won Kyung Chung

Sang Sic Yoon

Chang Ki Baek

Jung Taek You

Hong Joo Song

In Tae Kim

Chae Sung Lim

Woongrae Kim

Dong Hee Han

Jong Ho Son

Kyu Dong Hwang

Chul Moon Jung

Duck Hwa Hong

Jin Ho Jeong

Jun Yong Song

Kwang Hun Lee

Jae Woong Yun

Hyun Sik Jeong

Ki Up Kim

Man Keun Kang

Yoonna Oh

Byeong Yong Go

Seong Seop Lee

Seong Nyuh Yoo

Byoung Chul Lee

Hoiju Chung

A memory system includes: a memory controller configured to: issue a normal refresh command and a refresh management command, and adjust, based on a replacement counting value, an issuance frequency of at least one of the normal refresh command and the refresh management command; and a memory device configured to: perform a first refresh operation corresponding to the normal refresh h command and a second refresh operation corresponding to the refresh management command, and replace the second refresh operation with the first refresh operation according to a memory information signal, count a number of times of the replacing to generate the replacement counting value, and provide the replacement counting value.

Memory device for performing target refresh operation, memory system and operating method of memory system

An electronic system includes a controller configured to output a command, external row addresses, and external column addresses, receive a flag signal, and output the flag signal to a host. The electronic system also includes a semiconductor device configured to correct an error of internal data output from a memory cell selected based on the command, the external row addresses, and the external column addresses to output error-corrected internal data as data, and output the flag signal that is enabled when correcting the error in the internal data a set number of times.

Electronic system for monitoring error of address

A semiconductor system includes a controller configured to apply a command address, a first chip selection signal, and a second chip selection signal, and a semiconductor device including a first rank and a second rank configured to calibrate each termination resistance, based on the command address, the first chip selection signal, and the second chip selection signal.

Semiconductor device related to calibrating termination resistance

A semiconductor system includes a controller configured to transmit a command address and a plurality of read strobe signals, and a semiconductor device including a first rank and a second rank that are configured to receive the command address and the plurality of read strobe signals and to perform a write operation and a read operation based on the command address. In the semiconductor device, the first rank is configured to calibrate a termination resistance value of the first rank to a target resistance value when a write operation for the first rank is performed. In the semiconductor device, the first rank is configured to calibrate the termination resistance value of the first rank to a dynamic resistance value based on the plurality of read strobe signals when a write operation for the second rank is performed.

Semiconductor device related to calibrating a termination resistance

A memory device may include: a memory bank comprising a plurality of memory blocks, each divided into a normal area and a row hammer area, a command control circuit suitable for performing an access operation on the normal area in response to an active command, an internal command generation circuit suitable for generating an internal command in response to a precharge command, a target address generation circuit suitable for saving a count for each logic level combination of a received address in the row hammer area by performing an access operation on the row hammer area in response to the internal command, and setting an address corresponding to the count as a target address when the count satisfies a preset condition, and a refresh control circuit suitable for controlling a smart refresh operation on the target address.

Memory device for performing smart refresh operation by counting received address

A semiconductor memory apparatus may include: a memory cell array; an ECC (Error Check and Correction) circuit configured to detect an error from data read from the memory cell array in response to a read command, correct the detected error, and output an error correction signal whenever an error is corrected; and an EF (Error Flag) generator configured to enter a flag output mode when the number of times that the error correction signal is generated during a monitoring period reaches a threshold, and output the error correction signal as an error flag in the flag output mode.

Semiconductor memory apparatus and operation method of the semiconductor memory apparatus, and memory system having the semiconductor memory apparatus

A semiconductor device may include a data storage region, a parity storage region and an error correction circuit. The data storage region may be configured to store first data and second data. The parity storage region may be configured to store a parity. The error correction circuit may be configured to correct an error of the first data or an error of the second data and the parity, based on a transmission selection signal.

Semiconductor devices

A semiconductor device may include an inversion control signal generation circuit, a pattern control signal generation circuit, and a data input/output (I/O) circuit. The inversion control signal generation circuit may generate an inversion control signal according to a logic level combination of bit patterns included in at least one of a first address and a second address. The pattern control signal generation circuit may generate a pattern control signal from a pre-control signal in response to the inversion control signal. In response to the pattern control signal, the data input/output (I/O) circuit may generate data signals that will be output to an internal I/O line based on data signals loaded on a local I/O line.

A semiconductor device may include a syndrome generation circuit and a failure detection circuit. The syndrome generation circuit may generate a syndrome signal corresponding to a pattern of an output data signal. The failure detection circuit may detect the syndrome signal and sequentially store the syndrome signal to generate a first syndrome signal and a second syndrome signal if an error is detected from the syndrome signal. The failure detection circuit may generate a failure detection signal which is enabled if a logic level combination of the first syndrome signal is different from a logic level combination of the second syndrome signal.

A driving signal control circuit includes a discharge circuit, a counter circuit, and a control circuit. The discharge circuit is configured to compare a monitored voltage and a reference voltage, and generate a discharge signal. The monitored voltage is proportional to a core voltage. The counter circuit is configured to perform an up/down count operation according to the discharge signal, and generate a count signal. The control circuit is configured to generate a driving signal which has an enable period proportional to the count signal.

Driving signal control circuit and driving apparatus

A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output set signals. The second semiconductor device may generate a start signal in response to the set signals, generate an input control code and an output control code from the set signals in response to the start signal, generate a frequency determination signal including information on an operation frequency in response to the output control code, and control an internal operation in response to the frequency determination signal.

Semiconductor devices and semiconductor systems including the same

A sense amplifier driving device, and more particularly, a technology for improving the post overdriving operation characteristic of a semiconductor device. A sense amplifier driving device includes a driving signal generation block configured to compare a reference voltage set by a voltage trimming signal and a level of a power supply voltage, and generate a pull-up driving signal for controlling an operation of a sense amplifier; and a sense amplifier driving block configured to supply a driving voltage to a pull-up power line of the sense amplifier for an active operation period in correspondence to the pull-up driving signal, the driving signal generation block including a voltage divider configured to divide the power supply voltage, and output a divided voltage; and a voltage comparison section configured to compare the reference voltage and the divided voltage, and output a control signal for controlling an overdriving operation of the sense amplifier.

Sense amplifier driving device

A semiconductor device may include a first channel provided in a first die. The semiconductor device may include a second channel provided in a second die and disposed adjacent to the first channel, and configured to exchange signals and data with the first channel. The first channel and the second channel may receive and output calibration-related signals from and to each other through bonding, and may share calibration start signals. The calibration start signal may be respectively generated in the first channel and the second channel.

Semiconductor device

A temperature sensor includes: a gate voltage generation unit including a bias resistor, a first source resistor, and a first MOS transistor and configured to generate a gate voltage; and a variable voltage output unit including an output resistor, a second source resistor, and a second MOS transistor and configured to generate the variable voltage.

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Suwon-si, South Korea

Saeng Hwan Kim