Apple Inc.

Saeed Chehrazi

Feng Zhao

Wei Deng

Ali Parsa

Navid Lashkarian

Robert K Kong

Cristian Marcu

Chunwei Chang

In a computer system, a phase-locked loop circuit may generate a clock signal using a reference signal. The phase-locked loop circuit may include a programmable divider stage that includes multiple divider stages. When a frequency calibration is initiated on the phase-locked loop circuit, a control circuit may generate a pause signal in response to one or more of the divider stages reaching a particular logic state. The programmable divider stage may hold the one or more of the divider stages in the particular logic state using the pause signal.

Divider control and reset for phase-locked loops

Systems and method for improving operation of a radio frequency system are provided. One embodiment provides a radio frequency system that includes an amplifier device with a first data path and a second data path. Additionally, the radio frequency system includes a controller that instructs the radio frequency system to transmit a calibration signal, which includes a first portion that excites the first data path and a second portion that excites the second data path; determines time skew between the first and second data paths based at least in part on phase shift between a first sample of a feedback signal and the first portion, phase shift between a second sample of the feedback signal and the second portion, or both; and instructs the radio frequency system to adjust delay applied on the first data path, the second data path, or both based at least on the time skew.

Radio frequency time skew calibration systems and methods

Growing community of inventors

Irvine, CA, United States of America

Saeed Chehrazi