Analog Devices,inc.

Analog Devices International Unlimited Company

Anatog Devices, Inc.

Saeed Aghtar

Reza Alavi

Jian Wang

Yong Wang

Esha John

Hyman Shanan

Abdelaziz Chihoub

Haijiao Fan

Christoph M Steinbrecher

Kenneth J Keyes

Arathi Sundaresan

Aspects of this disclosure relate to a segmented receiver for a wireless communication system. The segmented receiver includes a first receiver segment and a second receiver segment configured to receive respective radio frequency signals. The radio frequency signals can be orthogonally polarized. Branch circuits in each receiver segment can provide a radio frequency signal to different mixers. The different mixers can be included in different receiver segments and receive local oscillator signals from independent local oscillators. Each receiver segment can process a different bandwidth of the radio frequency signal. Two different bandwidths of the radio frequency signal can be processed concurrently by different receiver segments.

Segmented receiver for wireless communications

Apparatuses and methods related to digital mobile radio (DMR) with enhanced transceiver are disclosed herein. The transceiver detects waveforms of signals received by a digital mobile station radio (MS). By detecting whether the waveforms of the signals, the transceiver allows a digital baseband processor of the MS to remain in a sleep state while the signals are being detected by the DMR, thereby reducing an amount of power used while the signals are being detected.

Digital mobile radio with enhanced transceiver

Provided herein are apparatus and methods for wideband receivers. In certain configurations, a radio frequency (RF) communication system includes two or more receiver slices that operate in parallel with one another to process an RF input signal. The receiver slices generate digital signals by processing different sub-bands of the RF input signal. For example, the RF communication system can include a first receiver slice that processes a first sub-band of the RF input signal and that generates a first digital signal representing the first sub-band, and a second receiver slice that processes a second sub-band of the RF input signal and generates a second digital signal representing the second sub-band. The RF communication system further includes a clock generation circuit that generates one or more clock signals to control timing of the receiver slices, and a sub-band processing circuit that processes the digital signals from the receiver slices.

Apparatus and methods for wideband receivers

A method of operating a radio frequency transceiver may include generating, by a transmit circuit of the transceiver, in-phase (I) and quadrature (Q) analog signals based on a digital calibration signal; mixing, by the transmit circuit, the I and Q analog signals with local oscillator (LO) and phase shifted LO signals to generate upconverted I and Q signals, the LO signal having a first frequency, and combining the upconverted I and Q signals to generate a combined signal; and converting, by a receive circuit of the transceiver, a signal based on the combined signal to a received digital signal using a sampling rate at a second frequency, the second frequency being less than the first frequency, wherein the converting downconverts frequency content in the combined signal.

Circuits and systems for transmitter calibration

Embodiments of the present invention may provide a signal processor with a wide gain range. The signal processor may comprise at least a discrete step gain stage and a continuous variable gain amplifier (VGA) stage. The discrete step gain stage may comprise a programmable gain amplifier (PGA) (e.g., low noise amplifiersand(LNAand LNA)). The VGA stage may provide a continuous range to compensate the LNAs gain steps. In one embodiment, the AGC controller enables an inherent hysteresis with the AGC step change if required.

RF AGC control

A sample and hold circuit architecture samples using two capacitors that are cyclically switched between charge and discharge modes. The sample and hold circuit includes a buffer to receive an input signal to be sampled, a first sampling capacitor, a second sampling capacitor, and an amplifier. The first sampling capacitor is connected to the output of the buffer during the positive phase of a clock and across the feedback path of the amplifier during the zero phase of the clock. The second sampling capacitor is connected to the output of the buffer during the zero phase of the clock and across the feedback path of the amplifier during the positive phase of the clock. Neither the first sampling capacitor nor the second sampling capacitor is simultaneously connected to the buffer, the amplifier, or to each other.

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Hillsborough, NJ, United States of America

Saeed Aghtar