Advanced Micro Devices Corporation

Ati Technologies Ulc

Ati Technologies Inc.

Ati International Srl

Pine Valley Investments, Inc.

Saeed Abbasi

Martin E Perrigo

Nima Gilanpour

Michael Foxcroft

Carol A Price

Raymond S P Tam

Michael A Nix

Steven A Steckler

Thomas Y Wong

Fangxing Wei

George A W Guthrie

Vincent Law

A phase locked loop (PLL) includes a first loop, a second loop, and a lock detector. The first loop locks a feedback signal having a frequency equal to a fraction of a frequency of an output signal to a reference signal in phase. The first loop has a first bandwidth. The second loop locks the feedback signal to the reference signal in frequency and has a second bandwidth. The first bandwidth is higher than the second bandwidth. The lock detector is coupled to the second loop and increases the second bandwidth in response to detecting that the feedback signal is not locked to the reference signal.

Phase locked loop with bandwidth control

The loop bandwidth of a PLL is adjusted based on a difference between the output signal of the PLL and the PLL reference signal. In an embodiment, the DC open loop gain and natural frequency of the PLL are adjusted based on the phase difference between the output signal and the reference signal, so that the loop bandwidth of the PLL is increased when the phase difference is outside a programmable range and is decreased when the phase difference is within the programmable range.

Phase lock loop with adaptive loop bandwidth

An amplifier circuit includes a first stage and a second stage. The first stage includes a differential input circuit coupled to a differential input node. The first stage includes a first partial cascode circuit including devices of a first type, the first partial cascode circuit being coupled to a first power supply node, a first bias node, and the differential input stage. The first stage includes a second partial cascode circuit including devices of a second type, the second partial cascode circuit being coupled to a second power supply node and the differential input circuit. The second stage is coupled to the first stage. The second stage includes a first full cascode circuit coupled to an output node.

Partial cascode in combination with full cascode operational transconductance amplifier

An integrated circuit includes a feedback controlled clock generating circuit, such as a DLL, PLL or other suitable circuit, that is operative to provide a feedback reference frequency signal based on a generated output clock signal. The integrated circuit also includes a programmable fine lock/unlock detection circuit that includes programmable static phase error sensitivity logic that senses phase error. The programmable static phase error sensitivity logic sets a phase lock sensitivity window used to determine a fine lock/unlock condition of the generated output clock signal. The programmable fine lock/unlock detection logic is also operative to generate a fine phase lock/unlock signal based on the set phase lock sensitivity window. The integrated circuit may also include a coarse lock detection circuit that generates a coarse lock signal based on a frequency unlock condition.

Programmable fine lock/unlock detection circuit

An oscillator. The oscillator includes a first ring oscillator having a first plurality of inverters, a first plurality of capacitors each having a first terminal coupled to an output terminal of a corresponding one of the first plurality of inverters, a second ring oscillator having a second plurality of inverters, and a second plurality of capacitors each having a first terminal coupled to an output terminal of a corresponding one of the second plurality of inverters. A second terminal of the first plurality of capacitors is coupled to an output terminal of a corresponding one of the second plurality of inverters. A second terminal of the second plurality of capacitors is coupled to an output terminal of a corresponding one of the first plurality of inverters. The oscillator is configured to provide as an output a differential clock signal.

Complementary ring oscillator with capacitive coupling

An apparatus includes a filter module, an amplification module, and an adjustment signal source. The filter module generates a filtered signal based on a received signal. This filtered signal has a level shift corresponding to a difference between a direct current (DC) level of the filtered signal and a DC level of the received signal. From the filtered signal and an adjustment signal, the amplification module generates an amplified signal. The adjustment signal, which is provided by the adjustment signal source, may control (e.g., diminish) an effect of the level shift on a DC level of the amplified signal.

Signal adjustment techniques

A delay locked loop (DLL) circuit having gain control is presented. The DLL circuit includes a bias generator responsive based on an error signal to produce first and second bias voltages to control a plurality of differential delay elements. The bias generator includes a bias current generator having a fixed voltage-controlled current source and a dynamic voltage-controlled current source to generate a bias current, and a bias voltage generator for receiving the bias current and generating first and second bias voltages. The bias generator can generate multiple current levels in different modes of operation. Each of the current levels of the bias generator allows a small range of currents and therefore small values of gain factors (K). Low Kvalues leads to lower jitter and better control over feedback stability, resulting in an increase in the range of operational frequencies.

Gain control circuitry for delay locked loop circuit

A phase locked loop (PLL) circuit adjusts a voltage controlled differential oscillator to generate an output frequency signal that is a selected multiple of an input reference signal. An oscillator control circuit increases and decreases the output frequency signal. A frequency detector detects a phase shift between the reference signal and the PLL output signal and produces an error signal. In response to the error signal, a fast lock circuit detects when the output frequency signal passes the selected multiple of the reference signal.

Current biased phase locked loop

A delay-locked loop for outputting a precisely signal relative to an input reference signal includes a plurality of selectively controlled delay elements and a delay element control circuit, including a phase detector for detecting a phase shift between the input reference signal and the delayed output signal and producing an error signal. Each of the delay elements includes a first input associated with a negative output and a second input associated with a positive output, whereby the positive and negative outputs are selectively coupled to a constant voltage source responsive to a first bias voltage and to a ground. The positive and negative outputs are responsive to a second bias voltage and the first and second voltage inputs. The constant voltage source and the positive output are coupled via a first transistor and the constant voltage source and negative output are coupled via being a second transistor.

Common-bias and differential structure based DLL

A delay lock loop (DLL) circuit for generating a precisely delayed output signal relative to an input signal. The DLL circuit includes a phase detector for detecting a phase difference between the input signal and the DLL output signal, a lock circuit for detecting when the difference between the input signal and the output signal is zero, and a delay element control circuit for increasing and decreasing the phase of the output signal. This circuit design reduces processing delay, improves jitter performance, and extends the DLL operating frequency range.

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Narberth, PA, United States of America

Saeed Abbasi