Kabushiki Kaisha Toshiba

Sadayuki Yoshitomi

Takashi Yamada

Tsuneaki Fuse

Shigeru Kawanaka

Tomoaki Shino

Makoto Yoshimi

Kazumi Inoh

Hideaki Nii

Naoki Wakita

Yuka Itano

Fumie Fujii

Mamoru Terauchi

A circuit simulation apparatus according to an embodiment of the present invention calculates a set value of a SPICE parameter of a MOSFET to carry out a variation analysis on a semiconductor circuit including the MOSFET. The apparatus includes a storage part configured to store an intermediate model expression that includes a variable related to a manufacture condition or device structure of the MOSFET as a variable affecting variation characteristics of the MOSFET, the intermediate model expression being formed with a universal function having a physical correlation between a physical amount defined by the variable and the SPICE parameter, a setting part configured to set information about the variable included in the intermediate model expression, a calculation part configured to calculate the set value of the SPICE parameter by using the information set in the setting part and the intermediate model expression stored in the storage part, and an output part configured to output process variation dependency of the semiconductor circuit.

Variation distribution simulation apparatus and method, and recording medium

In one embodiment, a SPICE corner model generating method for generating a SPICE corner model of an MOSFET includes preparing a table of a ratio X regarding a combination of two kinds of MOSFETs selected from N kinds of MOSFETs, the ratio X being a magnitude of a variation of an MOSFET in a case where directions of variations of the two kinds of MOSFETs are opposite directions to a magnitude of a variation of an MOSFET in a case where the directions of the variations of the two kinds of MOSFETs are the same direction, where N is an integer of 2 or greater. The method further includes reading out, when a combination of two kinds of MOSFETs is designated among the N kinds of MOSFETs, a value of the ratio X corresponding the designated combination from the table of the ratio X. The method further includes forming two kinds of corner models of opposite directional variations, the two kinds of corner models including a first corner model generated by applying the value of the ratio X to a fast-side corner of a first MOSFET of the two kinds of MOSFETs and to a slow-side corner of a second MOSFET of the two kinds of MOSFETs, and a second corner model generated by applying the value of the ratio X to a slow-side corner of the first MOSFET and to a fast-side corner of the second MOSFET.

Spice corner model generating method and apparatus

A method of extracting an equivalent circuit of a T-type transmission circuit measures signals of the first and second terminals to obtain S parameters, converts the S parameters into Z parameters to generate a T-type circuit by using the Z parameters, obtains first to third lead line resistors and first to third lead line inductors in the T-type circuit based on the Z parameters corresponding to constants of the T-type circuit, subtracts the Z parameters corresponding to the T-type circuit from the Z parameters corresponding to all of the equivalent circuit to calculate the Z parameters of a &#x3c0;-type circuit, converts the Z parameters of the &#x3c0;-type circuit into the Y parameters, and calculates first to third coupling capacitances based on the Y parameters.

Apparatus and method of extracting equivalent circuit of T-type transmission circuit

In a bipolar transistor improved to exhibit an excellent high-frequency property by decreasing the width of the intrinsic base with without increasing the base resistance, an emitter region, intrinsic base region and collector region are closely aligned on an insulating layer, and the intrinsic base region and the collector region make a protrusion projecting upward from the substrate surface. The protrusion has a width wider than the width of the intrinsic base region.

Lateral bipolar transistor formed on an insulating layer

In a lateral bipolar transistor, its emitter region, base region, link base region, and so forth, are made in self alignment with side walls of masks by using partly overlapping two mask patterns. Therefore, not relying on the mask alignment accuracy, these regions are made in a precisely controlled positional relation. Thus, the lateral bipolar transistor, thus obtained, is reduced in parasitic resistance of the base and parasitic junction capacitance between the emitter and the base, and alleviated in variance of characteristics caused by fluctuation of the length of a link base region, length of the emitter-base junction and relative positions of the emitter and the collector, and can be manufactured with a high reproducibility.

Growing community of inventors

Tokyo, Japan

Sadayuki Yoshitomi