Micron Technology Incorporated

Elpida Memory, Inc.

Hitachi, Ltd.

Ps4 Luxco S.a.r.l.

Renesas Eastern Japan Semiconductor, Inc.

Sadayuki Okuma

Yukihide Suzuki

Takahiro Koyama

Minoru Someya

Toshio Miyazawa

Hiroshi Ikeda

Yasushi Takahashi

Hiromasa Noda

Hiroshi Ichikawa

Hiroki Miyashita

Takao Ono

Atsushi Masumizu

Morihiko Mouri

Yosihiro Sakaguchi

Disclosed herein is an apparatus that includes a data terminal, a memory cell array, a mode register storing a plurality of operation parameters, and an output circuit configured to output, in response to a read command, an incorrect data to the data terminal instead of a correct data read from the memory cell array when a predetermined one of the operation parameters indicates a test mode.

Computer system with redundancy having fail test mode

A refresh tracking circuit and associated methods are disclosed herein. The tracking circuit may be configured to track a primary count value and a secondary count value based on addresses associated with received commands. The primary and secondary count values may be configured to control corresponding refresh operations respectively associated with a primary address and a secondary address.

Apparatus with a row-hammer address latch mechanism

Compensating for offsets in buffers and related systems, methods, and devices are disclosed. An apparatus includes buffers, control circuitry, and fuses. Each of the buffers includes an output and an offset adjustment input. Each of the buffers is controllable to adjust a direct current offset of an output voltage potential responsive to an offset adjustment code provided to the offset adjustment input. The control circuitry includes sets of offset latches. The offset adjustment input of each of the buffers is operably coupled to a different one of the sets of offset latches. Each set of offset latches is configured to provide the offset adjustment code to the offset adjustment input of a corresponding buffer. The fuses are configured to provide the offset adjustment code to each of a subset of the sets of offset latches.

Compensating offsets in buffers and related systems, methods, and devices

An apparatus includes an address bus configured to convey a command address; a primary address latch connected to the address bus and configured to latch a first address; a primary counter connected to the primary address latch and configured to track a primary count value when the command address matches the first address; and a secondary counter connected to the primary counter and configured to update a secondary count value when the primary count value reaches a primary threshold.

Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes an input pad, an input buffer including a first input node and a second input node, a switch that couples the first input node and the second input node in an active state and further decouples the first input node and the second input node in an inactive state, a control circuit that provides a signal causing the switch to be in the active state or an inactive state. The first input node of the input buffer is coupled to the input pad by a conductive wiring.

Apparatus of offset voltage adjustment in input buffer

A semiconductor device includes at least two semiconductor chips each including a plurality of data input/output pads, a data memory portion structured so as to read/write data through the plurality of data input/output pads, a test result input/output pad, and a test circuit for controlling a first test mode that decides data read from the data memory portion and outputs the decision from the test result input/output pad and a second test mode that decides data read from the data memory portion, inputs test result of another semiconductor chip from the test result input/output pad and outputs a synthesized test result of the test result of the chip itself and the test result of the other semiconductor chip from a specified part of the plurality of data input/output pads, and a plurality of data input/output terminals each connected with different data input/output pads.

Semiconductor device

A semiconductor device includes a plurality of memory mats, each of which includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells that are arranged at intersections of the word lines and the bit lines, and a plurality of dummy word lines, each of which is sandwiched between two corresponding ones of the word lines; a main dummy word line to which the dummy word lines included in the memory mats are commonly electrically connected; and a dummy-word-line control circuit that detects an electric potential of the main dummy word line when a test signal is activated, and outputs an error signal when the electric potential exceeds a predetermined threshold value. According to the present invention, because an electric potential of each of the dummy word lines is directly detected, an address of the word line, which has a short circuit with the dummy word line, can be reliably detected in a short time.

Semiconductor device and test method thereof

A semiconductor device includes a plurality of first data input/output terminals, a plurality of second data input/output terminals, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip includes a plurality of first data input/output pads connected with the first data input/output terminals, a first test circuit, and a first memory portion. The first test circuit generates a first test result in response to a data output from the first memory portion at a test operation. The second semiconductor chip includes a plurality of second data input/output pads connected with the second data input/output terminals, a second and a third test circuits, and a second memory portion. The second test circuit generates a second test result in response to a data output from the second memory portion, and the third test circuit generates a third test result in response to the second test result and the first test result input from the first test circuit of the first semiconductor chip and outputs the third test result from a specified second data input/output terminal.

Semiconductor device including first semiconductor chip including first pads connected to first terminals, and second semiconductor chip including second pads connected to second terminals

In a semiconductor memory device, a repair circuit includes mode fuses to select one of plural repair modes corresponding to plural kinds of defects, respectively. The semiconductor memory device can repair a defective memory cell having operational margin defect without using redundancy memory cells.

Semiconductor memory device including a repair circuit which includes mode fuses

It is an object of the present invention to realize a circuit diagram creating method and circuit diagram creating apparatus capable of efficiently acquiring information on a lower layer, and a circuit diagram creating method for creating a layered electric circuit diagram from data indicating an electric circuit that includes the steps of determining an outline area to be displayed from wiring information and graphics information which are data indicating the electric circuit for symbol graphics of a lower layer and displaying information on the circuit diagram so as not to go beyond the outline area.

Apparatus and method for creating circuit diagram, program therefor and recording medium storing the program

A package for mounting a semiconductor device has a surface exposed to an atmosphere. The exposed surface is covered with a covering material such as a paint, a tape or a seal.

Package for mounting semiconductor device

Disclosed a semiconductor memory device in which an access to a memory cell is designated according to a command, and a common data terminal is used as an input terminal to which a write signal to the memory cell is input and an output terminal from which a read signal from the memory cell is output. The semiconductor memory device includes: a first input circuit having input capacitance corresponding to the input terminal to which the command is input; and a second input circuit having input capacitance corresponding to the data terminal. A mask signal for checking the write signal input from the data terminal is input by either the first or second input circuit by a bonding option technique.

Growing community of inventors

Tokyo, Japan

Sadayuki Okuma